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Hi, "Node libs/gui/xopendisplay/cflags is required but provided detection callback fails to find tha...
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Binoy B

over 3 years ago
Hi, "Node libs/gui/xopendisplay/cflags is required but provided detection callback fails to find that feature on system".. this is the error iam getting while trying to compile xschem. Iam using ubuntu 20.04. Any help?
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Hello everyone, when I run qflow on my verilog design it creates a folder named "layout" where you h...
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Mudasir

over 2 years ago
Hello everyone, when I run qflow on my verilog design it creates a folder named "layout" where you have .gds and .mag files which you can open in magic and view, however when I try to do this then I do not see the standard cell gates and on the console window it says that it is unable to read them, what could be the issue.
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Is there a way to launch the OpenRoad GUI using openlane makefiles so that it includes the STA const...
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Matthew Guthaus

over 2 years ago
Is there a way to launch the OpenRoad GUI using openlane makefiles so that it includes the STA constraints? (I'm not sure if this is "built in"... I know I could do it through scripting...)
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Hi all, Any ideas to solve my hold violation problem? ```Antenna Summary: Source: /project/openlane/...
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manili

almost 4 years ago
Hi all, Any ideas to solve my hold violation problem?
Antenna Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/41-antenna.rpt
Number of pins violated: 25
Number of nets violated: 25
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/26-spef_extraction_sta.min.rpt.
[INFO]: Calculating Runtime From the Start...
[INFO]: flow failed for user_proj_example/2021.10.31_13.43.15 in 0h27m31s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example
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Hey all, I am having trouble installing klayout on my Ubuntu 24. I just used “sudo apt install klayo...
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SURYA RC

over 1 year ago
Hey all, I am having trouble installing klayout on my Ubuntu 24. I just used “sudo apt install klayout” and when I “klayout -v” it outputs “Klayout 0.28.15” However when I try to open klayout by “klayout”, it runs a few processes and then proceeds to say core has been dumped. I tried to install from the klayout website, but I keep hitting dependencies issues with libgit2-1.1, libruby3.0 and libpython3.10
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Does anyone know how I can open klayout with the pdk? I am trying with the following command:
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Juan Andres

over 2 years ago
Does anyone know how I can open klayout with the pdk? I am trying with the following command:
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Stefano: OpenSTA can do power analysis
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Lofty

over 4 years ago
Stefano: OpenSTA can do power analysis
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Hello. I'm using xschem with gf180mcu PDK. There are many digital stdcells I can use in xschem with ...
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Junbeom Park

over 2 years ago
Hello. I'm using xschem with gf180mcu PDK. There are many digital stdcells I can use in xschem with SKY130 PDK. But I couldn't find them in xschem with gf180mcu PDK. Should I manually design latches, flip-flops, etc. to use them? or is there any sources that I can use in xschem? Thank you for reading my question.
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<@U01819B63HP>, I was looking to do mixed signal simulation in xschem. I was wondering if there is a...
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Deepak

over 1 year ago
@Stefan Schippers, I was looking to do mixed signal simulation in xschem. I was wondering if there is a way to import verilog(.v) file in xschem or can i create verilog file in xschem and is there any documentation for writing verilog code in xschem??
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Can someone help me with the LVS code error? My config file and error description files: [STEP 42] [...
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steven darker

almost 2 years ago
Can someone help me with the LVS code error? My config file and error description files: [STEP 42] [INFO]: Running LVS (log: ../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log)... [ERROR]: There are LVS errors in the design: See '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/reports/signoff/42-neuron_core_dffram.lvs.rpt' for a summary and '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log' for details. [ERROR]: Step 42 (lvs) failed with error: -code 1 -level 0 -errorcode NONE -errorinfo { while executing "throw_error" (procedure "quit_on_lvs_error" line 13) invoked from within "quit_on_lvs_error -rpt $count_lvs_rpt -log $log" (procedure "run_lvs" line 76) invoked from within "run_lvs" (procedure "run_lvs_step" line 10) invoked from within "run_lvs_step"} -errorline 1
42-lvs.lef.log42-neuron_core_dffram.lvs.rptconfig.json
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