Hi, I'm a student who just started with IC design. Since the school provides Cadence tools for free, I'm currently using Virtuoso for schematic design and simulation with the Sky130 PDK (currently using

efabless/main

from Github). What I want to simulate is a simple

nfet

simulation, but I keep encountering many errors. Since the Spectre simulator supports both Spectre and Spice, I thought it would work without issue. I know Sky130 is friendly to the open-source tools, but is it intentionally incompatible with Virtuoso? Does anyone have any insights or comments on this? Please share your experiences with getting it to work with Virtuoso. I would greatly appreciate any advice on the Sky130 PDK ecosystem and its compatibility with Cadence tools.

Hello everyone I want to create a blockage at some empty area in my design is it possible to create the blockage and what is command. Can anyone help with this

Hi all, Any ideas to solve my hold violation problem?

Antenna Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/41-antenna.rpt
Number of pins violated: 25
Number of nets violated: 25
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/26-spef_extraction_sta.min.rpt.
[INFO]: Calculating Runtime From the Start...
[INFO]: flow failed for user_proj_example/2021.10.31_13.43.15 in 0h27m31s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example

New Fet parameter annotator is added in sky130. Shows

gm, gds, vth, vdsat, cgg, cgdo, cgso

and

ft

, calculated as

ft = gm / [2π (Cgg + Cgdo + Cgso)]

All the necessary procedures are in the sky130

xschemrc

file, since all this is pdk-specific (plus the

sky130_fd_pr/annotate_fet_params.sym

symbol). Next step is to add similar functionality for the IHP PDK if there interest. @Harald Pretl I have verified thet the

ft

calculated with the above formula is correct (of course i was not questioning the formula but the ngspice

cg*

parameters), i have run an AC analysis and let ngspice show the point where unity current gain occurs. The frequency value matches with the formula as shown in the video.

I am doing some experimentation with fine grained clock gating and would love to use the openlane flow to test it out. However, I can't find much info about how well supported clock gating is. I tried synthesizing a bunch of registers with a synchronous enable signal, essentially this:

wire ena;
wire[8:0] data;
wire ena_reg;
wire[8:0] data_reg;
always @(posedge clk) begin
    ena_reg <= ena;
end
always @(posedge clk) begin
    if (ena) begin
        data_reg <= data;
    end else begin
        data_reg <= data_reg;
    end
end

Synthesizing this with the default

flow.tcl

generates multiplexers to select the next value, which is not what I want. I have tried the same thing on ice40 FPGAs using yosys and there it correctly does "clock gating" (it uses the enable pins on the registers) Is clock gating like this even supported by openlane? Do I have to turn it on somehow? From searching around I've found that there is a clock gating cell:

sky130_fd_sc_hd__dlclkp_1

but I have no idea how I'd begin to try and use that

I'm currently testing the OSU FreePDK 45nm with the simple test design 'spm'. I'm encountering large no. of errors during the SPICE export and DRC check steps of the flow inspite of getting 0 violations after routing. Any idea what could be the cause of the error? I have attached the config.tcl, magic_spice.log and magic_drc.log for your reference. Kindly look into it.

@Stefan Schippers I am facing issue in simulating DFF cell from sky130 standard cell library in xschem. Can you please suggest what might be wrong in this testbench.

Hi everyone! I'm trying to integrate a large analog macro with gsg pads into the user_project_wrapper. However, when it tries placing the macro, it gives the error that the macro is taller than any row (the macro class used in lef file in this case is CORE, and it's dimensions are 140 um x 400 um). I've tried adding some obstruction layers using GRT_OBS but that doesn't seem to do anything, and I've also tried changing the macro's class from CORE to BLOCK but then it fails while generating the PDN. Does anybody know what variables I need to change to make it go through multiple rows, and prevent PDN and other routing generation steps inside the macro's area? Any help would be appreciated. Thanks!

Hello everyone, I was trying to analyze the corner impact on the circuit and I need to plot transient waveforms in different corners. I would appreciate it if anyone let me know how should I do that in xschem. Also, where can I find the script for plotting ngspice signals in matlab? Thanks @Tim Edwards

Hi there, I'm running into the following error when simulating a synthesized design with ngspice (netlist attached)...

tom@tom:~/repos/projects/openwave$ ngs pll tb_pfd
setup_tcp_xschem: problems listening to TCP port: 2021
couldn't open socket: address already in use


Note: Compatibility modes selected: hs a

Warning: m=xx on .subckt line will override multiplier m hierarchy!


Circuit: 

Error: unknown subckt: x1.xfiller_13_144.x0 vdd x1.xfiller_13_144.a_124_375# x1.xfiller_13_144.a_36_472# vdd x1.xfiller_13_144.pfet_06v0 <http://x1.xfiller_13_144.ad|x1.xfiller_13_144.ad>=1.0736p x1.xfiller_13_144.pd=6.64u <http://x1.xfiller_13_144.as|x1.xfiller_13_144.as>=0.5368p <http://x1.xfiller_13_144.ps|x1.xfiller_13_144.ps>=3.32u x1.xfiller_13_144.w=1.22u l=1u
    Simulation interrupted due to error!

Note: No ".plot", ".print", or ".fourier" lines; no simulations run

I have the following included in my top level spice dec but it still seems to be unable to find the 6v fets as far as i can tell

.include "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/design.ngspice"
.lib "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical
.lib "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/smbb000149.ngspice typical"

Anyone have any ideas? Thanks in advance, Tom