open-source-silicon.dev

bba.JPG

bank.spice

dd.JPG

inverter_blo_mag.spice

Does anyone know how I can correct my test bench to simulate a design taken from magic with a subcircuit?

Where is the inverter subcircuit's spice file?

as the subcircuit is flattened, the transistors appear in the spice

The subcircuit has only two terminals, VDD and GND. The other terminals aren't listed.

```X0 vout1 vout3 GND GND inverter_blo
X1 vout2 vout1 GND GND inverter_blo
X2 vout3 vout2 GND GND inverter_blo
X3 vout3 vout2 VDD VDD inverter_blo
X4 vout1 vout3 VDD VDD inverter_blo
X5 vout2 vout1 VDD VDD inverter_blo```
It has four terminals here in your testbench file. That is why it doesn't run.

You should use

`X0 VDD GND inverter_blo`

if I just call GND and VDD, which I think is what comes out of the block, it simulates but everything stays at 0, even though I initialize to 0

You should start any inner node with a preset voltage. Use

```.ic X0.vout1 = 1```

Your transient command should be:

```tran 0.1n 50n 0.1n uic```

Yes that worked, but this command "nodeset x2.vout3=0" its same?

I don't know if it works for transient simulations. It should. But it should not be set as 0, I think. nodeset and ic act different. Nodeset is too find the solution for OP and DC, but I don't know if it works as a initial condition for transient sims.

Well, I used nodeset with conditional 0, and it also works

Good. Just be aware that for a real design, you must consider the width of the metal tracks, as they may not be able to handle the current.

inverter_blo.mag

<@U01QTMG2K8R> Do you know how I can instantiate the block, taking into account that it has 9 outputs?

it is the name of the instance, begining with x, then the names of each node at each pin, then the name of the subcircuit.