So I have something here kind of confusing me and would like to ask for your opinion: I have two AC responses with similar magnitude plot with -20dB/dec before ft. The first one is a very stable system with a pole around 1e4 Hz and PM of ~90 degree. The second plot, however, for some reason has a terrible PM, but what bothers me is that it has clearly only one pole before ft (as -20dB/dec) but the phase plot does not match this at all! What could be the reason behind this? Thanks!

Could be a doublet of a LHP pole and RHP zero. They cancel in the magnitude response, but give you 180 degrees phase shift.

Nope. The first one is not an stable system. It doesn't have 90° phase margin. It is approx. -270°. Use cphase instead of phase to calculate it. Anyway, we don't know which circuit you're simulating.

I verified that with

PZ

analysis and yes there is an RHP zero ~ 3.7e4 Hz canceled with an LHP pole ~ 2.8e4 Hz. I further verified their stability in transient analysis and yes the second situation circuit oscillated. Guess I need to push that RHP zero to the left plane somehow. More often I see a zero-pole pair (or doublet in closed-loop) as an LHP pole + an LHP zero but not with an RHP zero. Miller compensation without a null resistor generates an RHP zero, parasitic Cgd has a RHP zero; are there in general other situations where this LHP pole + an RHP zero occurs? Thanks.

Ok, what you need could be only make some changes to your circuit first. I'm guessing you should increase the current of the second stage of your amplifier. Maybe even use some kind of active frequency compensation.

If you want help, you need to show what your circuit is. It's hard to diagnose a black box.

The circuit was an LDO with folded cascode EA. I have attached the pictures in the following (sorry the machine I was using before did not have

xschem

installed). The first schematic is EA, the second one is EA with the PMOS pass transistor, and the last one is the loop stability testbench of the LDO. In the pictures I attached before, the first one is at which the load current is 10mA and the second is load current=10uA. It has a stability problem when the load current is small. Sorry if those wire connections are messy as I am still changing things back and forth.

I think you can see from textbook equations why the RHP zero from the Miller cap is close to the second pole for low load current (low gm in the second stage).

So what I knew was since the zero of the miller cap with null resistor is (about) 1/(2*pi*Cc*(1/gm2-Rf)) and when gm2 is low zero shift back to the RHP again, therefore I would re-adjust the value for Rf to keep it to LHP which so far did not help that much. I probably need to do a more in-depth analysis and see what is going on...

My suggestion is to not shift the zero into the LHP, but just push it to infinity. One general problem you have (for low current) is that both your dominant and non dominant poles are very close, so the typical analysis used in textbooks falls apart (using the dominant pole approximation to factor the poles).

I do also realize that the RHP zero is probably from the large PMOS pass transistor (1/(Cgd*1/gm2)) which is always moving together with the second pole (output of LDO)...

True

First of all, test the DC conditions for your circuit. In this case, it should be the minimum and maximum output current loads. Does it work for zero current load? Most LDO designs I see there is a resistive voltage divider at VREG, so it is not directly connected at the amplifier input. It is a problem for the actual layout, because the transistor gates should be not connected directly to very large metal tracks. Look for antenna effect. Try to use a simple differential pair as your amplifier first. It has a very small output range, but it could be good for tests. Later, switch back to your folded cascode. It has a good output range, but it has non dominant poles that can be causing problems in your design.

As Chris pointed out, the main culprit at low current is likely the large Cgd of the PMOS. It leads to a RHP zero near the non dominant pole and together they destroy the phase margin. The large nulling resistor does not help. To prove this, I'd add a cap of value -Cgd in parallel and see if the problem goes away.