That depends on the workload of a chip and on the margins you have. For digital chips you usually count the flipflops and multiply it by an estimated toggle rate. In Kunal's course I learnt that some of the situations where it can more likely fail would be counters that overflow, huge clocktrees that switch at the same time, ... There are complex power simulation tools that can simulate the power behavior of a whole chip which we might want to try some day. E.g. overclockers sometimes add/increase such capacitors, so that the calculations are still correct even when more power is demanded.