#357 dummy metal 1 connections in sky130_fd_io__signal_5_sym_hv_local_5term cause LVS mismatch. Issue created by d-m-bailey The spice file in the PDK was modified with the following comment.

* Modified by Tim:  The resistors here are in an annular shape, and they overlap
* between cells such that the center of the resistor connects between the two
* devices.  To be correct, these two nets must come out as pins.

.SUBCKT sky130_fd_io__signal_5_sym_hv_local_5term GATE IN NBODY NWELLRING VGND net16
*.PININFO GATE:I IN:B NBODY:B NWELLRING:B VGND:B
XI1 IN GATE VGND NBODY sky130_fd_pr__esd_nfet_g5v0d10v5 m=1 w=5.4 l=0.6 mult=1
+ sa=0.0 sb=0.0 sd=0.0 topography=normal area=0.048 perim=0.94
* RI9 net18 NBODY short
* RI8 net16 NWELLRING short
RI9 net18 NBODY sky130_fd_pr__res_generic_m1 W=0.02 L=0.005
RI8 net16 NWELLRING sky130_fd_pr__res_generic_m1 W=0.02 L=0.005
.ENDS sky130_fd_io__signal_5_sym_hv_local_5term

Looking at the actual layout, it appears that resistors do not overlap as expected. I believe this means that the 6th terminal should not be connected in the parent source subckt. Currently, they are all shorted to

VCC_IO

in

sky130_fd_io__gpio_buf_localesd

and similarly in other subckts that instantiate this cell.

* Modified by Tim:  The local_5term cells have resistors that overlap, and the resistor
  * end terminals must be added to the netlist to make it correct.
  
  .SUBCKT sky130_fd_io__gpio_buf_localesd IN_H OUT_H OUT_VT VCC_IO VGND
  + VTRIP_SEL_H
  *.PININFO IN_H:I OUT_H:O OUT_VT:O VCC_IO:B VGND:B VTRIP_SEL_H:I
  Xesd_res_q0 IN_H OUT_H sky130_fd_io__res250only_small
  Xggnfet2_q0 VGND OUT_VT VGND VCC_IO VGND VCC_IO
  + sky130_fd_io__signal_5_sym_hv_local_5term
  Xggnfet6_q0 VGND VCC_IO VGND VCC_IO OUT_H VCC_IO
  + sky130_fd_io__signal_5_sym_hv_local_5term
  Xggnfet5_q0 VGND VCC_IO VGND VCC_IO OUT_VT VCC_IO
  + sky130_fd_io__signal_5_sym_hv_local_5term
  Xggnfet1_q0 VGND OUT_H VGND VCC_IO VGND VCC_IO
  + sky130_fd_io__signal_5_sym_hv_local_5term
  Xhv_passgate_q0 OUT_H VTRIP_SEL_H OUT_VT VGND sky130_fd_pr__nfet_g5v0d10v5 m=1
  + w=3.0 l=1.0 mult=1 sa=0.265 sb=0.265 sd=0.28 topography=normal area=0.063
  + perim=1.14
  .ENDS sky130_fd_io__gpio_buf_localesd

Changing the

net16

in

RI8

to a unique signal (eg.

net16_

) results in a match. However, the run time goes from 10 min to 44 min. (edit: changing the last

VCC_IO

to

VCC_IO_

in the parent instance causes the increase in run time - with or without the

net16

->

net16_

change. Just changing

net16

to

net16_

results in a match in under 4 min.) RTimothyEdwards/open_pdks