Hi everyone, when writing an SDC file for OpenLane...
# timing-closure
d
Hi everyone, when writing an SDC file for OpenLane, is there a way to get a pin or instance by it's hierarchical path name? This is how I am used to accessing pins when I have set up constraints for a Cadence design flow. For example, in my design, I have a top level
mp_serializer_top
, which contains the instance
serializer_inst
, which has a pin
dest_clk_i
. I have tried the following commands:
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get_pins "serializer_inst/dest_clk_i"
get_pins "serializer_inst.dest_clk_i"
get_pins -hsc "/" "serializer_inst/dest_clk_i"
get_pins "\\serializer_inst/dest_clk_i"
get_pins "mp_serializer_top/serializer_inst/dest_clk_i"
get_pins "\\mp_serializer_top/serializer_inst/dest_clk_i"
However, they all fail (saying pin cannot be found) Also, when I try to see a list of all pins with
get_pins *
, it returns:
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_9031d90700000000_p_Pin _2033d90700000000_p_Pin _7033d90700000000_p_Pin ...
as if the design has been flatted and all original names removed. So I don't even have an example of what a correct pin name is. When looking at SDC scripts posted by others on this channel, it seems like accessing pins in this way is commonly done... What am I missing? Any help appreciated, thank you!
m
get_pins returns a collection of pin pointers in text form. You have to use get_name on such an object to get the name. You should look at the verilog coming out of yosys to see what the name look like (they are often mangled).
d
Thank you! I tried this out, and figured out that what I actually was looking for was:
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[get_name [get_nets -hier "serializer_inst.dest_clk_i"]]
However, this particular case still does not work because apparently each net can only be accessed by one name. Which appears to be the highest point in the hierarchy the net reaches. So since my design looks like it does below, only the net name
clk_i
exists, but not
serializer_inst.dest_clk_i
or
serializer_inst.tree_inst.clk_i
.
Is there any way to access the nets/pins at the edges of specific modules in my design? My design has many clock dividers and I would like to write an SDC script to iteratively create a generated clock on each of their outputs. The problem is that some of the divider output clocks go to different levels of the design, so the net names of the clocks don't follow a regular pattern...
m
OpenROAD operates on a flat netlist today so you can't see the intermediate hierarchies. We are working on adding support. Standalone sta can handle that if you only need it for signoff
d
Okay good to know. Thank you for explaining!