@Tim Edwards Where could I find the cross section for the diodes? I am a bit confused by the layout, since it seems like everything inside the guard ring is electrically connected (when I press s for the center box, everything inside the guard ring gets selected). The diode in the image is the sky130_fd_pr__diode_pw2nd_05v5. Thanks again

The guard ring is the thin line around the border and is made of P+ diffusion in substrate (identified by a "pwell" layer in the layout, but it's just the bare substrate). It's the substrate itself that forms the P side of the diode, which is underneath the entire diode diffusion area. The guard ring contacts just sink the current. The area you have selected is the N-diffusion, which forms the N side of the diode. There is a contact array on top of this, the details of which are hidden in magic's view (what you see is a "contact area"). The P-N junction is the entire bottom side of the N diffusion where it meets the substrate.

So in this case the guard ring is the anode and the middle diode contact is the cathode? Does this mean if we were to use an n-diode the anode would have to be grounded?

@Emmi Wyttenbach: What does the extracted netlist look like?

pdiode_100.spice

Okay, that's pretty much exactly what I have for the extracted diode, and I get the trace in your 2nd plot, with current reaching around 600mA at 5V forward bias. Which of your plots is which?

The first plot is what I'm getting for the extracted diode, and the second is what I get when I instantiate a diode directly in xschem.

I didn't create the symbol. I'm getting from the extracted layout what you got for the xschem-derived netlist. The problem must be in your testbench connections to the extracted diode. What does your testbench netlist look like?

Sorry I meant how did you create a testbench using the extracted layout?

I just wrote a testbench by hand. Your problem here is that you have used "@pinlist" in the symbol, so it will output the pins for the diode in whatever order it uses by default. So you are getting a netlist where the cell

pdiode_100

is being instantiated in the netlist with a port order that is different from the one generated by extraction from magic. The tools (xschem and magic) are independent, so they don't know what the other one is doing, and because the diode is defined in the PDK as a subcircuit, there's no obvious order for the pins. Your two choices are: (1) Use the "@@" notation in the format line of the symbol to declare the port names individually, and make them match the order in the layout (2) Use the "port index" command in magic to set the port indexes in the order that they are being output by xschem.

Sorry could you clarify the syntax for the first choice you listed? Are you saying instead of @pinlist I should say @@? I might also be missing something else in my setup because I suspected something was wrong with the pin assignment, so I tried all possible configurations of connection from the symbol to VDD/GND and this was the only result I got with nonzero current

It should just be

format="@name @@p_side @@n_side @@psub @symname"

(I'm unable to see from your screenshots what you named the pins in xschem, so I'm assuming the same names

p_side

,

n_side

, and

psub

that you used in the layout).

What could be other possible sources of error? I'm still getting the same plot as before

Make sure you understand where the final netlist that is being simulated is located, and what its contents are. There is only one issue here, which is pin ordering. If you change your DC sweep from (0 to 5) to (-5 to 0) you should see the diode curve (in reverse).

This is how I defined the pins in my symbol (and how I named the 3 pins accordingly). The order is the same as in the spice file. I did just try changing the DC sweep to be from -5 to 0 and the results did not change. If it were just a pin ordering issue, it seems that I should be able to try all possible configurations for connecting the 3 pins to vdd/gnd and one of them should work, but I tried this to make sure and none of them displayed a diode curve

This is my .mag file (top level and parameterized device layout), the netlist extracted from layout, and the testbench netlist (written by hand, not with xschem). If you run ngspice on

pdiode_test_tb.spice

you should get a normal-looking diode curve (you may need to change the path in the .lib line in the testbench netlist first).

I think I figured out the problem. My version of magic still appends the units to the end (area=1e+14p instead of area=1e+14), so when I used the spice list in the simulation the dimensions were off

I don't think the issue is in magic. The newer version of magic was just changing the format to be more obvious at a glance (e.g., "1e+2" instead of "1e+14p") but the values themselves didn't change. The difference should be in the

sky130A.tech

file for magic, where the diode devices should be described like this:

# NOTE: SkyWater diode models have bizarre units requiring bizarre scaling
 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6

This tech file has a "version" section at top with:

version 1.0.376-6-g3f9bdbd

which means that it was created by open_pdks version 1.0.376. The diode area and perimeter values were corrected in open_pdks version 1.0.350 (October 27, 2022).

Oh ok got it. Thank you so much for all your help!

Sorry for spending so much time barking up the wrong tree.

No problem! The information on pin ordering was very useful (and just helped us solve issues with another circuit)