https://open-source-silicon.dev logo
Channels
aa
abcc
activity
adiabatonauts
analog-design
announce
announcements
b2aws
b2aws-tutorial
bag
basebands
beagleboard
bluetooth
board-respin
cadence-genus
cadence-innovus
cadence-spectre
cadence-virtuoso
caravan
caravel
caravel-board
chilechipmakers
chip-yard
chipignite
chipignite2206q_stanford_bringup
chisel
coalition-for-digital-environmental-sustainability
community_denmark_dtu
containers
courses
design-review
design-services
dffram
digital-design
digital-electronics-learners
discord-mods
dynamic-power-estimation
efabless
electric
events
fasoc
fault
foss-asic-tools
fossee-iitb-esim
fossee-iitb-google-sky130
fpga
funding
fuserisc
general
generative-ai-silicon-challenge
genius-vlsi
gf180
gf180mcu
hardware-beginners
help-
ieee-sscs-cac-23
ieee-sscs-dc-21q3
ieee-sscs-dc-22
ieee-sscs-dc-23
ihp-sg13g2
images
infiniband
j-core
japan-region
junk
klayout
latam_vlsi
layouteditor
lvs
lvs-analysis
magic
magical
maker-projects
maker-zone
microwatt
mpw-2-silicon
mpw-one-clean-short
mpw-one-silicon
neuro-mem
nydesign
open_pdks
open-pdk
openadiabaticlogic
openfpga
openhighqualityresonators
openlane
openlane_cloudrunner
openlane-development
openocd
openpositarithmetic
openpower
openram
openroad
opentitan
osu
pa-test-chip
paracells
pd-openlane-and-sky130
picosoc
pll
popy_neel
power
private-shuttle
rad-lab-silicon
radio
rdircd
reram
researchers
rf-mmw-design
rios
riscv
sdram
serdes
shuttle
shuttle-precheck
shuttle-status
silicon-photonics
silicon-validation
silicon-validation-private
sky130
sky130-ci
sky130-pv-workshop
sky65
sky90
skywater
sram
stdcelllib
strive
swerv
system-verilog-learners
tapeout-job
tapeout-pakistan
team-awesome
timing-closure
toysram
travis-ci
uvm-learners
vendor-synopsys
venn
verification-be
verification-fe
verilog-learners
vh2v
vhdl
vhdl-learners
vliw
vlsi_verilog_using_opensource_eda
vlsi_verilog_using_opensoure_eda
vlsi-learners-group
vlsi101
waveform-viewers
xls
xschem
xyce
zettascale
Powered by
Title
c

Chris

03/01/2023, 7:36 PM
Hi @Stefan Schippers I remember we were talking about the resistance value for sky130 pdk a while ago. I have another quick question regarding the layout aspect of
res_xhigh_po
which is a generic version high resistance polysilicon resistor that takes more generic geometric
W
values. When I go to magic and try to find out the layout for
res_xhigh_po
I do not think I have found any pcell for that, only the ones available are those 0.35, 0.69, 1.41, etc. However, those pcells the
W
seems editable and can take other values. I have not done any LVS yet but wondering what is the most convenient way to have a resistor layout that is LVS/DRC clean but can take arbitrary
L
and
W
values? Thanks. Also, I know you can make
mult
to be some integers meaning they are placed in parallel, how about if I want multiple of them in series?
t

Tim Edwards

03/02/2023, 4:04 PM
I can answer that: (1) There are only fully officially characterized models for the
res_high_po
at those specific widths, which correspond to the exact device width that precisely fits 1 to 5 contacts on the terminals. The idea, I think, is that it is hard to gauge the exact resistance of the terminal area for any arbitrary contact geometry, so they fabricated and measured five devices and produced models to match what they measured. The
res_xhigh_po
device, on the other hand, was introduced with sky130 and was only experimental in s8, and I expect has not been completely characterized (at least not in the sky130 PDK). Its model is not as sophisticated as
res_high_po
, and the width-specific models just call the generic model with a specific width. Out of concern for the fact that the sky130 DRC rules insist that
res_xhigh_po
devices must exist in only the five "approved" widths, I followed that convention. The simple
res_xhigh_po
device model divides the device width by the contact pitch to get the number of contacts, but it does not try to determine the effect of the remainder of poly on the sides of the contact when the width does not exactly match the contact pitch, so the value will be slightly off if the device width isn't one of the "approved" widths. I could easily add the generic base model to magic's device generator script. But if you just draw the layer type
xpolyres
in magic and contact both ends with layer type
xpc
, then it will extract as generic type
res_xhigh_po
. (2)
M
is the SPICE parameter for multiple devices.
mult
is a parameter used for mismatch simulation, for the obscure reason that you can't use the value
M
inside model equations in SPICE. So
mult
is supposed to be set equal to
M
and is multiplied by the square root of the device area to get the variance for mismatch calculation. I think that there are versions of SPICE that understand
S
as a series multiplier, or maybe it's just dependent on a subcircuit model being defined with an
S
parameter, but regardless, ngspice and the sky130 models don't support that. However, if you use netgen for LVS, it will combine resistors in series to match layout against schematic, so you can just specify the total length in xschem (but, going back to the discussion of terminal resistance above, the total resistance of ten resistors in series can be quite different from the resistance of one resistor multiplied by ten, so be aware of that in your design).
c

Chris

03/02/2023, 7:37 PM
This is very informative, thanks a lot! Despite not being characterized, I do have applications where I have to use very high-resistance resistors so
res_xhigh_po
becomes my choice. I am using
res_xhigh_po_0p35
with a
L
equals 20. Are there any concerns regarding having too big of
L
? Thanks.