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Andras Tantos

03/01/2023, 7:16 PM
Hi! My name is Andras Tantos and I'm new to these forums, so please let me know if I ask the wrong question in the wrong place. I have a project that I try to get synthesized on the OpenLane flow. The flow (more or less) succeeds, but fails timing closure. When I look at the 11-cts_rsz_sta.rpt file, I get path reports like this: =========================================================================== report_checks -unconstrained ============================================================================ Startpoint: 16382 (rising edge-triggered flip-flop clocked by clk') Endpoint: dram_addr[1] (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 5.00 5.00 clock clk' (rise edge) 0.00 5.00 clock source latency 0.08 0.06 5.06 v clk (in) 1 0.04 clk (net) 0.08 0.00 5.06 v clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16) 0.04 0.17 5.23 v clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0_clk (net) 0.04 0.00 5.24 v clkbuf_1_1_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.14 5.37 v clkbuf_1_1_0_clk/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_1_0_clk (net) 0.03 0.00 5.37 v clkbuf_1_1_1_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.04 0.15 5.52 v clkbuf_1_1_1_clk/X (sky130_fd_sc_hd__clkbuf_8) 2 0.02 clknet_1_1_1_clk (net) 0.04 0.00 5.52 v clkbuf_2_2_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.04 0.15 5.67 v clkbuf_2_2_0_clk/X (sky130_fd_sc_hd__clkbuf_8) 2 0.02 clknet_2_2_0_clk (net) 0.04 0.00 5.67 v clkbuf_3_4_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.19 0.28 5.96 v clkbuf_3_4_0_clk/X (sky130_fd_sc_hd__clkbuf_8) 17 0.18 clknet_3_4_0_clk (net) 0.19 0.00 5.96 v clkbuf_leaf_91_clk/A (sky130_fd_sc_hd__clkbuf_16) 0.05 0.24 6.20 v clkbuf_leaf_91_clk/X (sky130_fd_sc_hd__clkbuf_16) 18 0.05 clknet_leaf_91_clk (net) 0.05 0.00 6.20 v _08138_/A (sky130_fd_sc_hd__buf_1) 0.05 0.12 6.32 v _08138_/X (sky130_fd_sc_hd__buf_1) 1 0.01 03255 (net) 0.05 0.00 6.32 v clkbuf_0__03255_/A (sky130_fd_sc_hd__clkbuf_16) 0.03 0.16 6.48 v clkbuf_0__03255_/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0__03255_ (net) 0.03 0.00 6.48 v clkbuf_1_1__f__03255_/A (sky130_fd_sc_hd__clkbuf_16) 0.04 0.15 6.63 v clkbuf_1_1__f__03255_/X (sky130_fd_sc_hd__clkbuf_16) 5 0.02 clknet_1_1__leaf__03255_ (net) 0.04 0.00 6.63 v _08991_/A (sky130_fd_sc_hd__buf_1) 0.09 0.14 6.77 v _08991_/X (sky130_fd_sc_hd__buf_1) 1 0.01 04038 (net) 0.09 0.00 6.77 v clkbuf_0__04038_/A (sky130_fd_sc_hd__clkbuf_16) 0.03 0.17 6.94 v clkbuf_0__04038_/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0__04038_ (net) 0.03 0.00 6.94 v clkbuf_1_0__f__04038_/A (sky130_fd_sc_hd__clkbuf_16) 0.05 0.16 7.10 v clkbuf_1_0__f__04038_/X (sky130_fd_sc_hd__clkbuf_16) 6 0.04 clknet_1_0__leaf__04038_ (net) 0.05 0.00 7.10 v _13735_/A (sky130_fd_sc_hd__buf_1) 0.06 0.12 7.22 v _13735_/X (sky130_fd_sc_hd__buf_1) 1 0.01 07471 (net) 0.06 0.00 7.22 v clkbuf_0__07471_/A (sky130_fd_sc_hd__clkbuf_16) 0.03 0.16 7.38 v clkbuf_0__07471_/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0__07471_ (net) 0.03 0.00 7.38 v clkbuf_1_1__f__07471_/A (sky130_fd_sc_hd__clkbuf_16) 0.04 0.16 7.53 v clkbuf_1_1__f__07471_/X (sky130_fd_sc_hd__clkbuf_16) 5 0.03 clknet_1_1__leaf__07471_ (net) 0.04 0.00 7.53 v _13737__23/A (sky130_fd_sc_hd__inv_2) 0.02 0.04 7.57 ^ _13737__23/Y (sky130_fd_sc_hd__inv_2) 1 0.00 net59 (net) 0.02 0.00 7.57 ^ _16382_/CLK (sky130_fd_sc_hd__dfxtp_1) 0.03 0.30 7.87 v _16382_/Q (sky130_fd_sc_hd__dfxtp_1) 1 0.00 bus_if.u170_output_port[1] (net) 0.03 0.00 7.87 v _08163_/A1 (sky130_fd_sc_hd__mux2_4) 0.11 0.34 8.21 v _08163_/X (sky130_fd_sc_hd__mux2_4) 1 0.05 03270 (net) 0.12 0.01 8.23 v _08164_/A (sky130_fd_sc_hd__buf_6) 0.03 0.16 8.38 v _08164_/X (sky130_fd_sc_hd__buf_6) 1 0.01 net14 (net) 0.03 0.00 8.38 v output14/A (sky130_fd_sc_hd__buf_6) 0.04 0.14 8.52 v output14/X (sky130_fd_sc_hd__buf_6) 1 0.03 dram_addr[1] (net) 0.04 0.00 8.52 v dram_addr[1] (out) 8.52 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (propagated) -0.25 9.75 clock uncertainty 0.00 9.75 clock reconvergence pessimism -2.00 7.75 output external delay 7.75 data required time ----------------------------------------------------------------------------- 7.75 data required time -8.52 data arrival time ----------------------------------------------------------------------------- -0.77 slack (VIOLATED)
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Matt Liberty

03/01/2023, 8:37 PM
How was your output arrival constraint set?
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Vijayan Krishnan

03/02/2023, 6:00 AM
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Andras Tantos

03/11/2023, 1:03 AM
Oh, sorry, I'm new to slack as well and I didn't notice your comments up until now.
The only constraint I set is this one: "CLOCK_PERIOD": 10, in the projects' config.json file. Here's the complete json if that helps: { "DESIGN_NAME": "Pipeline", "DESIGN_IS_CORE": 0, "VERILOG_FILES": ["dir::../../verilog/rtl/pipeline.sv"], "CLOCK_PERIOD": 10, "CLOCK_PORT": "clk", "CLOCK_NET": "Pipeline.clk", "FP_SIZING": "absolute", "DIE_AREA": "0 0 900 600", "________FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "PL_BASIC_PLACEMENT": 0, "PL_TARGET_DENSITY": 0.55, "VDD_NETS": ["vccd1"], "GND_NETS": ["vssd1"], "DIODE_INSERTION_STRATEGY": 4, "RUN_CVC": 0, "pdk::sky130*": { "FP_CORE_UTIL": 45, "RT_MAX_LAYER": "met4", "scl:😒ky130_fd_sc_hd": { "CLOCK_PERIOD": 10 }, "scl:😒ky130_fd_sc_hdll": { "CLOCK_PERIOD": 10 }, "scl:😒ky130_fd_sc_hs": { "CLOCK_PERIOD": 8 }, "scl:😒ky130_fd_sc_ls": { "CLOCK_PERIOD": 10, "SYNTH_MAX_FANOUT": 5 }, "scl:😒ky130_fd_sc_ms": { "CLOCK_PERIOD": 10 } }, "pdk::gf180mcuC": { "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", "CLOCK_PERIOD": 24.0, "FP_CORE_UTIL": 40, "RT_MAX_LAYER": "Metal4", "SYNTH_MAX_FANOUT": 4, "PL_TARGET_DENSITY": 0.45 } }
Oh, apparently slack also finicky about 'enters'. Yet another apology. So, my original question - since it was cut off in the thread - is this: Can you help me in relating the entities in the list to the source code? As is, it is int terribly actionable on my side.
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Matt Liberty

03/11/2023, 5:14 AM
Is this intentionally a 1/2 cycle path? You have an inverter in the clock tree: _13737__23/Y (sky130_fd_sc_hd__inv_2)
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Andras Tantos

03/11/2023, 4:28 PM
Good catch, thank you! Indeed there are a few flops that are intentionally triggered on the negative edge.
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Matt Liberty

03/12/2023, 7:24 AM
This path is doomed. It arrives at the ff
7.57 ^ _16382_/CLK
and the required time is
7.75   data required time
so there is virtually no time for any logic to happen. I'm not sure what is intended here.
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Andras Tantos

03/12/2023, 3:34 PM
Thanks for the explanation. I think I have an idea now where to start poking. A follow-on question though: this design has no problem closing timing close to 100MHz on a MAX10 FPGA, so I thought in 130nm CMOS it should breeze through at 100MHz. Yet, it's not even close. Are there general rules I should follow to get better timing closure results within the OpenLane flow? What are the best practices, especially ones that are different from an FPGA-based environment? Thanks again!
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Matt Liberty

03/13/2023, 12:36 AM
I suspect your constraints are not correct more than anything is wrong per-se with the design.
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Andras Tantos

03/14/2023, 11:04 PM
Got it and thanks! Let me look at that topic and learn more about how constraints work in this flow (is there a documentation somewhere I should look at?) Thanks again! Andras
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Matt Liberty

03/15/2023, 5:54 PM
The reference timing docs are at https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf . There isn't a specific doc on writing constraints though the SDC format is industry standard so you can find commentary on the web. Is this a case where you can provide the design?
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Andras Tantos

03/15/2023, 10:21 PM
Great, thank you for all the help!