Hi! My name is Andras Tantos and I'm new to these forums, so please let me know if I ask the wrong question in the wrong place. I have a project that I try to get synthesized on the OpenLane flow. The flow (more or less) succeeds, but fails timing closure. When I look at the 11-cts_rsz_sta.rpt file, I get path reports like this: =========================================================================== report_checks -unconstrained ============================================================================ Startpoint: 16382 (rising edge-triggered flip-flop clocked by clk') Endpoint: dram_addr[1] (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 5.00 5.00 clock clk' (rise edge) 0.00 5.00 clock source latency 0.08 0.06 5.06 v clk (in) 1 0.04 clk (net) 0.08 0.00 5.06 v clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16) 0.04 0.17 5.23 v clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0_clk (net) 0.04 0.00 5.24 v clkbuf_1_1_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.14 5.37 v clkbuf_1_1_0_clk/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_1_0_clk (net) 0.03 0.00 5.37 v clkbuf_1_1_1_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.04 0.15 5.52 v clkbuf_1_1_1_clk/X (sky130_fd_sc_hd__clkbuf_8) 2 0.02 clknet_1_1_1_clk (net) 0.04 0.00 5.52 v clkbuf_2_2_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.04 0.15 5.67 v clkbuf_2_2_0_clk/X (sky130_fd_sc_hd__clkbuf_8) 2 0.02 clknet_2_2_0_clk (net) 0.04 0.00 5.67 v clkbuf_3_4_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 0.19 0.28 5.96 v clkbuf_3_4_0_clk/X (sky130_fd_sc_hd__clkbuf_8) 17 0.18 clknet_3_4_0_clk (net) 0.19 0.00 5.96 v clkbuf_leaf_91_clk/A (sky130_fd_sc_hd__clkbuf_16) 0.05 0.24 6.20 v clkbuf_leaf_91_clk/X (sky130_fd_sc_hd__clkbuf_16) 18 0.05 clknet_leaf_91_clk (net) 0.05 0.00 6.20 v _08138_/A (sky130_fd_sc_hd__buf_1) 0.05 0.12 6.32 v _08138_/X (sky130_fd_sc_hd__buf_1) 1 0.01 03255 (net) 0.05 0.00 6.32 v clkbuf_0__03255_/A (sky130_fd_sc_hd__clkbuf_16) 0.03 0.16 6.48 v clkbuf_0__03255_/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0__03255_ (net) 0.03 0.00 6.48 v clkbuf_1_1__f__03255_/A (sky130_fd_sc_hd__clkbuf_16) 0.04 0.15 6.63 v clkbuf_1_1__f__03255_/X (sky130_fd_sc_hd__clkbuf_16) 5 0.02 clknet_1_1__leaf__03255_ (net) 0.04 0.00 6.63 v _08991_/A (sky130_fd_sc_hd__buf_1) 0.09 0.14 6.77 v _08991_/X (sky130_fd_sc_hd__buf_1) 1 0.01 04038 (net) 0.09 0.00 6.77 v clkbuf_0__04038_/A (sky130_fd_sc_hd__clkbuf_16) 0.03 0.17 6.94 v clkbuf_0__04038_/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0__04038_ (net) 0.03 0.00 6.94 v clkbuf_1_0__f__04038_/A (sky130_fd_sc_hd__clkbuf_16) 0.05 0.16 7.10 v clkbuf_1_0__f__04038_/X (sky130_fd_sc_hd__clkbuf_16) 6 0.04 clknet_1_0__leaf__04038_ (net) 0.05 0.00 7.10 v _13735_/A (sky130_fd_sc_hd__buf_1) 0.06 0.12 7.22 v _13735_/X (sky130_fd_sc_hd__buf_1) 1 0.01 07471 (net) 0.06 0.00 7.22 v clkbuf_0__07471_/A (sky130_fd_sc_hd__clkbuf_16) 0.03 0.16 7.38 v clkbuf_0__07471_/X (sky130_fd_sc_hd__clkbuf_16) 2 0.02 clknet_0__07471_ (net) 0.03 0.00 7.38 v clkbuf_1_1__f__07471_/A (sky130_fd_sc_hd__clkbuf_16) 0.04 0.16 7.53 v clkbuf_1_1__f__07471_/X (sky130_fd_sc_hd__clkbuf_16) 5 0.03 clknet_1_1__leaf__07471_ (net) 0.04 0.00 7.53 v _13737__23/A (sky130_fd_sc_hd__inv_2) 0.02 0.04 7.57 ^ _13737__23/Y (sky130_fd_sc_hd__inv_2) 1 0.00 net59 (net) 0.02 0.00 7.57 ^ _16382_/CLK (sky130_fd_sc_hd__dfxtp_1) 0.03 0.30 7.87 v _16382_/Q (sky130_fd_sc_hd__dfxtp_1) 1 0.00 bus_if.u170_output_port[1] (net) 0.03 0.00 7.87 v _08163_/A1 (sky130_fd_sc_hd__mux2_4) 0.11 0.34 8.21 v _08163_/X (sky130_fd_sc_hd__mux2_4) 1 0.05 03270 (net) 0.12 0.01 8.23 v _08164_/A (sky130_fd_sc_hd__buf_6) 0.03 0.16 8.38 v _08164_/X (sky130_fd_sc_hd__buf_6) 1 0.01 net14 (net) 0.03 0.00 8.38 v output14/A (sky130_fd_sc_hd__buf_6) 0.04 0.14 8.52 v output14/X (sky130_fd_sc_hd__buf_6) 1 0.03 dram_addr[1] (net) 0.04 0.00 8.52 v dram_addr[1] (out) 8.52 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (propagated) -0.25 9.75 clock uncertainty 0.00 9.75 clock reconvergence pessimism -2.00 7.75 output external delay 7.75 data required time ----------------------------------------------------------------------------- 7.75 data required time -8.52 data arrival time ----------------------------------------------------------------------------- -0.77 slack (VIOLATED)

How was your output arrival constraint set?

Mostly they are using default sdc constraint https://github.com/The-OpenROAD-Project/OpenLane/blob/master/scripts/base.sdc

Oh, sorry, I'm new to slack as well and I didn't notice your comments up until now.

Is this intentionally a 1/2 cycle path? You have an inverter in the clock tree: _13737__23/Y (sky130_fd_sc_hd__inv_2)

Good catch, thank you! Indeed there are a few flops that are intentionally triggered on the negative edge.

This path is doomed. It arrives at the ff

7.57 ^ _16382_/CLK

and the required time is

7.75   data required time

so there is virtually no time for any logic to happen. I'm not sure what is intended here.

Thanks for the explanation. I think I have an idea now where to start poking. A follow-on question though: this design has no problem closing timing close to 100MHz on a MAX10 FPGA, so I thought in 130nm CMOS it should breeze through at 100MHz. Yet, it's not even close. Are there general rules I should follow to get better timing closure results within the OpenLane flow? What are the best practices, especially ones that are different from an FPGA-based environment? Thanks again!

I suspect your constraints are not correct more than anything is wrong per-se with the design.

Got it and thanks! Let me look at that topic and learn more about how constraints work in this flow (is there a documentation somewhere I should look at?) Thanks again! Andras

The reference timing docs are at https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf . There isn't a specific doc on writing constraints though the SDC format is industry standard so you can find commentary on the web. Is this a case where you can provide the design?

Great, thank you for all the help!