https://open-source-silicon.dev logo
Channels
aa
abcc
activity
adiabatonauts
analog-design
announce
announcements
b2aws
b2aws-tutorial
bag
basebands
beagleboard
bluetooth
board-respin
cadence-genus
cadence-innovus
cadence-spectre
cadence-virtuoso
caravan
caravel
caravel-board
chilechipmakers
chip-yard
chipignite
chipignite2206q_stanford_bringup
chisel
coalition-for-digital-environmental-sustainability
community_denmark_dtu
containers
courses
design-review
design-services
dffram
digital-design
digital-electronics-learners
discord-mods
dynamic-power-estimation
efabless
electric
events
fasoc
fault
foss-asic-tools
fossee-iitb-esim
fossee-iitb-google-sky130
fpga
funding
fuserisc
general
generative-ai-silicon-challenge
genius-vlsi
gf180
gf180mcu
hardware-beginners
help-
ieee-sscs-cac-23
ieee-sscs-dc-21q3
ieee-sscs-dc-22
ieee-sscs-dc-23
ihp-sg13g2
images
infiniband
j-core
japan-region
junk
klayout
latam_vlsi
layouteditor
lvs
lvs-analysis
magic
magical
maker-projects
maker-zone
microwatt
mpw-2-silicon
mpw-one-clean-short
mpw-one-silicon
neuro-mem
nydesign
open_pdks
open-pdk
openadiabaticlogic
openfpga
openhighqualityresonators
openlane
openlane_cloudrunner
openlane-development
openocd
openpositarithmetic
openpower
openram
openroad
opentitan
osu
pa-test-chip
paracells
pd-openlane-and-sky130
picosoc
pll
popy_neel
power
private-shuttle
rad-lab-silicon
radio
rdircd
reram
researchers
rf-mmw-design
rios
riscv
sdram
serdes
shuttle
shuttle-precheck
shuttle-status
silicon-photonics
silicon-validation
silicon-validation-private
sky130
sky130-ci
sky130-pv-workshop
sky65
sky90
skywater
sram
stdcelllib
strive
swerv
system-verilog-learners
tapeout-job
tapeout-pakistan
team-awesome
timing-closure
toysram
travis-ci
uvm-learners
vendor-synopsys
venn
verification-be
verification-fe
verilog-learners
vh2v
vhdl
vhdl-learners
vliw
vlsi_verilog_using_opensource_eda
vlsi_verilog_using_opensoure_eda
vlsi-learners-group
vlsi101
waveform-viewers
xls
xschem
xyce
zettascale
Powered by
Title
m

Matthew Guthaus

03/01/2023, 4:51 PM
Is it a requirement to provide source files for a project on the open MPW? This project from MPW8 does not: https://platform.efabless.com/projects/1881 It looks like they just uploaded a GDS file. Edit: Maybe it wasn't selected for the MPW8?
@Boris Murmann This says it was part of the PICO project? Does that require it to be open source?
b

Boris Murmann

03/01/2023, 4:59 PM
Yes, we have that requirement, but this design was not finished or taped out.
m

Matthew Guthaus

03/01/2023, 5:06 PM
Got it. Thanks for the quick response.
We were looking at all of the ReRAM arrays taped out to see the current status and saw that one.
m

Mitch Bailey

03/01/2023, 6:27 PM
@Matthew Guthaus The requirements for Google MPW state • The project must be fully open. The project must contain a GDSII layout, which must be reproducible from source contained in the project. However, there is no check for source files in the analog precheck and only a top level check in the digital precheck. Hopefully soon we are planning to add LVS to the precheck.
m

Matthew Guthaus

03/01/2023, 6:38 PM
Yes, I was mostly wondering if they actually get checked. Thanks for the added info.
t

Tim Edwards

03/01/2023, 6:42 PM
We are now starting an initiative to specify exactly what needs to be submitted for a successful analog design precheck. The general underlying idea is that any set of tools can be used for the design, but that the design GDS must be submitted along with a valid netlist, and that it must be possible to extract the GDS using Magic and run LVS against the netlist using Netgen and generate a correct LVS result. That will put a few constraints on the way analog projects can be made, mostly eliminating things that I consider to be bad design practices anyway, like splitting devices between subcells, that require the best commercial tools to bend over backwards to sort out and make a valid netlist from. The result, though, will be that for any submitted design GDS, anyone can use open source tools to simulate the design or otherwise be able to reuse it. It would be preferable to require a valid schematic, but that's rather more problematic to enforce.
👍 1
m

Matthew Guthaus

03/01/2023, 6:45 PM
That makes sense. While using commercial tools should be ok to make open IP, it really is a focus on open source.
t

Tim Edwards

03/01/2023, 6:45 PM
And more to the point, it's a focus on re-use, by people who may not have access to the same tools used by the original designer.
t

Tobias Strauch

03/02/2023, 10:04 PM
@Tim Edwards Forgive me if I’m wrong. But as a follow-up on a discussion we had a few weeks back, I realized in the meantime, that the netlist you check for is just the top level (hierarchical) netlist, not the flat one. So you check for a wrapper version with just another syntax than the RTL version. Sorry if I’m wrong, it’s been a while since my submission.
t

Tim Edwards

03/02/2023, 10:20 PM
@Tobias Strauch: Yes, I believe there is some existing netlist sanity check that is essentially useless (at best). I have no intention of keeping that check, but instead do a proper LVS in a way that is both meaningful and not too much of a burden on users who might have already done LVS but in a different flow using different tools.
t

Tobias Strauch

03/02/2023, 10:31 PM
Sure, but the check I'm refering to was added for 7 or 8, with the intension you kindly explained here: https://open-source-silicon.slack.com/archives/C017HPHCMEY/p1670278280743899?thread_ts=1670113972.314549&cid=C017HPHCMEY I just wanted to rise a flag that a hierarchical netlist version of the wrapper might not be what you were looking for. (Sorry again if I'm wrong.) Cheers.