We are now starting an initiative to specify exactly what needs to be submitted for a successful analog design precheck. The general underlying idea is that any set of tools can be used for the design, but that the design GDS must be submitted along with a valid netlist, and that it must be possible to extract the GDS using Magic and run LVS against the netlist using Netgen and generate a correct LVS result. That will put a few constraints on the way analog projects can be made, mostly eliminating things that I consider to be bad design practices anyway, like splitting devices between subcells, that require the best commercial tools to bend over backwards to sort out and make a valid netlist from. The result, though, will be that for any submitted design GDS, anyone can use open source tools to simulate the design or otherwise be able to reuse it. It would be preferable to require a valid schematic, but that's rather more problematic to enforce.