is there any documentation on adding new standard cell libraries?

thanks Kunal!

Or this one: https://github.com/iic-jku/SKY130-RTL-with-Custom-Standardcell-to-GDSII

I keep seeing people get tripped up on the need to produce a timing library for their new cells. Has anybody got a good solution for this?

Me not, unfortunately, but I would be interested in a solution.

The supplements in Weste & Harris have a utility called charlib. Charlib has this in the readme.

# CharLib README
# (c) 2003 David Harris
#
# This program characterizes a standard cell library.  It requires two
# user-created input files:
#
#  charlib.lst:  a list of gates to characterize with desired stimulus
#                the first gate must be the inverter with logical effort 1
#                see the charlib.lst example file for format information
#  netlist.hsp:  a file containing netlists of all the gates to characterize
#
# It also requires the charlib.hsp SPICE deck and a directory called archive.
# Finally, you need to have HSPICE and perl on your workstation and you
# must set your path to find HSPICE with the command "hspice".  You may have
# to edit the first line of charlib.pl to reflect the location of charlib
# on your system.

I’ve been thinking it could make a good starting place for something that characterizes cells with ngspice. The program can be found at http://pages.hmc.edu/harris/cmosvlsi/4e/code.html

This presentation from WOSET this year may be helpful: https://woset-workshop.github.io/Videos/2022/14-Nishizawa-long.mp4 (and is another characterizer which I think is viable in spite of presented results---I expect that it is as good as any other open-source characterizer available.) Also check the WOSET 2022 proceedings for

xcell

from Rajit Manohar's group at Yale (note that it is more oriented toward asynchronous circuits). Other people doing their own standard cell designs: James Stine (Oklahoma State University) and Staf Verhaegen (for the latter, see the presentation at FSiC 2022: https://wiki.f-si.org/index.php?title=PDKMaster_%26_co.:_a_framework_for_scalable_and_technology_portable_standard_cell,_IO_and_SRAM_libraries (The last two being general information for the thread, not specifically for Matt Venn, who did the lengthy interview with James and was at FSiC 2022.)