Matt Venn
02/28/2023, 1:28 PMKunal
02/28/2023, 1:44 PMMatt Venn
02/28/2023, 1:50 PMHarald Pretl
02/28/2023, 4:16 PMMatt Liberty
03/02/2023, 4:02 PMHarald Pretl
03/02/2023, 4:05 PMEric Smith
03/08/2023, 2:10 AM# CharLib README
# (c) 2003 David Harris
#
# This program characterizes a standard cell library. It requires two
# user-created input files:
#
# charlib.lst: a list of gates to characterize with desired stimulus
# the first gate must be the inverter with logical effort 1
# see the charlib.lst example file for format information
# netlist.hsp: a file containing netlists of all the gates to characterize
#
# It also requires the charlib.hsp SPICE deck and a directory called archive.
# Finally, you need to have HSPICE and perl on your workstation and you
# must set your path to find HSPICE with the command "hspice". You may have
# to edit the first line of charlib.pl to reflect the location of charlib
# on your system.
I’ve been thinking it could make a good starting place for something that characterizes cells with ngspice.
The program can be found at
http://pages.hmc.edu/harris/cmosvlsi/4e/code.htmlTim Edwards
03/13/2023, 1:43 AMxcell
from Rajit Manohar's group at Yale (note that it is more oriented toward asynchronous circuits).
Other people doing their own standard cell designs: James Stine (Oklahoma State University) and Staf Verhaegen (for the latter, see the presentation at FSiC 2022: https://wiki.f-si.org/index.php?title=PDKMaster_%26_co.:_a_framework_for_scalable_and_technology_portable_standard_cell,_IO_and_SRAM_libraries
(The last two being general information for the thread, not specifically for Matt Venn, who did the lengthy interview with James and was at FSiC 2022.)