In my synthesis stage I get a bunch of warnings that look like

Warning: multiple conflicting drivers for CombinationalFFT.\v.comb_fft.genblk2[2].fft_stage.genblk1[3].bfu_in.dc [31]:
    port Y[31] of cell $techmap\v.comb_fft.genblk2[2].fft_stage.genblk1[3].bfu_in.$add$./designs/sky130hd/CombinationalFFT/CombinationalFFT__pickled.v:756$137 ($add)
    port Y[31] of cell $techmap\v.comb_fft.genblk2[2].fft_stage.genblk1[3].bfu_in.$add$./designs/sky130hd/CombinationalFFT/CombinationalFFT__pickled.v:757$138 ($add)

Then my OpenROAD crashes with the error in the picture, even though the module in the specified line looks like this:

module ButterflyVRTL (
	clk,
	reset,
	recv_val,
	recv_rdy,
	send_val,
	send_rdy,
	ar,
	ac,
	br,
	bc,
	wr,
	wc,
	cr,
	cc,
	dr,
	dc
);
	parameter n = 32;
	parameter d = 16;
	parameter mult = 1;
	input wire clk;
	input wire reset;
	input wire recv_val;
	input wire send_rdy;
	input wire [n - 1:0] ar;
	input wire [n - 1:0] ac;
	input wire [n - 1:0] br;
	input wire [n - 1:0] bc;
	input wire [n - 1:0] wr;
	input wire [n - 1:0] wc;
	output wire send_val;
	output wire recv_rdy;
	output wire [n - 1:0] cr;
	output wire [n - 1:0] cc;
	output wire [n - 1:0] dr;
	output wire [n - 1:0] dc;
	reg [n - 1:0] ar_reg;
	reg [n - 1:0] ac_reg;
	wire mul_rdy;
	wire [n - 1:0] tr;
	wire [n - 1:0] tc;
	FpcmultVRTL #(
		.n(n),
		.d(d)
	) mul(
		.clk(clk),
		.reset(reset),
		.ar(br),
		.ac(bc),
		.br(wr),
		.bc(wc),
		.cr(tr),
		.cc(tc),
		.recv_val(recv_val),
		.recv_rdy(recv_rdy),
		.send_val(send_val),
		.send_rdy(send_rdy)
	);
	always @(posedge clk)
		if (reset) begin
			ar_reg = 0;
			ac_reg = 0;
		end
		else if (recv_rdy) begin
			ar_reg = ar;
			ac_reg = ac;
		end
		else begin
			ar_reg = ar_reg;
			ac_reg = ac_reg;
		end
	




	always @(*) begin 
		cr = ar_reg + tr;
		cc = ac_reg + tc;

		dr = ar_reg - tr;
		dc = ac_reg - tc;
	end
endmodule

Any idea on how to fix this? Thank you so much in advance!

I'm pretty sure you should use non-blocking assignment in your posedge clock block.

I tried changing the assignments to non-blocking and it still gives me similar warnings. I will try to use Verilator.

If you have access to a commerical tool like VCS or DC then that will help too. The specific error is triggered in yosys, so you can ask over there if you cannot find the source of the issue.

Sounds great! Thank you so much

Maybe we should get Austin in the C2S2 slack 🙂