Hi @Tim Edwards @Mitch Bailey. Excuse me, how to fix this Property errors were found for a two-parallel resistors, please? LVS is passed to two resistors as shown in Figure 1. However, when I am doing a parallel connection for those two resistors, property errors are found, as depicted in Figure 2. Is there an explanation for this or how to fix this property error?

Thanks @Ahmed Reda Looks like a series/parallel - parallel/series reduction problem. @Tim Edwards from

base/netgen.c

/*----------------------------------------------------------------------*/
/* Series and Parallel combination:                                     */
/* All devices of the same type that exist in series and parallel       */
/* combinations will be treated as a single device in a network.        */
/* Series connections are only allowed for resistors and inductors.     */
/* Any device may be connected in parallel.  For combinations of series */
/* and parallel, as in a resistor network, there is a set of rules:     */
/*                                                                      */
/* Running parallel and series checks:                                  */
/* 1. Run parallel once.  If a repeat run and no devices are merged,    */
/*    then go to 4.                                                     */
/* 2. Run series until no devices are merged.                           */
/* 3. If series ran more than once, then go to 1.                       */
/* 4. End merge                                                         */
/*                                                                      */
/* Each merge procedure, when it finds two devices that can be merged,  */
/* removes the second device from the netlist and adds its properties   */
/* to the first device.  If a series merge, then the nodes are adjusted */
/* appropriately.  Where A is the property list of the first device and */
/* B is the property list of the second device, the first and last      */
/* properties of A and the first property of B may require a marker to  */
/* indicate the topology of the network, as follows (in order):         */
/*                                                                      */
/* For a parallel merge:                                                */
/*    1) If A has series components then tag first property of A with   */
/*       "open" and tag first property of B with "close".               */
/*    2) If B has series components then tag first property of B with   */
/*       "open".                                                        */
/*                                                                      */
/* For a series merge:                                                  */
/*    1) If A has unbalanced "opens", then add "close" to first         */
/*       property of B to balance the "opens".                          */
/*    2) Always tag B with "series".                                    */
/*                                                                      */
/* Tags are indicated by a property named "_tag" which has a string     */
/* value of ordered characters, "+" for series, "(" for open, and ")"   */
/* for close.  A device with only one property record has no "_tag"     */
/* record.  A device which is in parallel with the device(s) in front   */
/* of it is implicitly parallel by not having an "+" tag, and may not   */
/* have a tag at all.                                                   */
/*                                                                      */
/* The property check routine is responsible for comparing device       */
/* series/parallel networks against each other.  Otherwise, each        */
/* series/parallel network is considered topologically as a single      */
/* device, and any differences in the series/parallel networks between  */
/* two circuits being matched will be treated as a property error.      */
/*----------------------------------------------------------------------*/

So the layout is a loop of 8 resistors, with none in parallel and all in series. The comment seems to indicate that series reduction will be performed until one device remains. The netlist is a loop of 2 resistors, these are reduced parallelly (new word) to one resistor. The

CombineSeries

routine needs to stop if it reduces to a parallel combination, but the function comment states

/*----------------------------------------------------------------------*/
/* Find all nodes that are connected to exactly two devices of the same */
/* class.  Where found, if the device is allowed to combine serially    */
/* (check properties), then remove the node and merge the devices into  */
/* one.                                                                 */
/*                                                                      */
/* This routine depends on CombineParallel() being run first so that no */
/* parallel devices are reported as series.                             */
/*                                                                      */
/* Return the number of devices merged.                                 */
/*----------------------------------------------------------------------*/

Maybe a parallel check is needed in

CombineSeries

. Another consideration (possible solution) is that ports should probably not be deleted during series reduction.

@Mitch Bailey Thank you. Do you mean that the series/parallel - parallel/series reduction problem can not be solved, till now? or should i hack a spice file to pass LVS without property errors? Is there a suggestion solution/script?

@Ahmed Reda: (1) Why is the schematic side listing the resistor width as 0.7? (2) What is the device type being used (xschem shows "res_xhigh_po" but that is a generic form and is not one of the layout device choices, normally). (3) Can you post the netlists and the LVS output?

@Tim Edwards Point (3) please check out the schematic net-list is

rpx1.spice

LVS output

comp.out

and gds

rpm1.gds

@Ahmed Reda Can you share your setup file and netgen commands?

@Mitch Bailey

netgen -batch lvs "rpm1.spice rpm1" "rpx1.spice rpx1" /home/ahmedreda/PDK/sky130A/libs.tech/netgen/sky130A_setup.tcl

@Ahmed Reda: One thing that you can do, as long as you have the individual resistors represented in the schematic, is to remove the parallel combination from the setup file (lines 63 to 66, and lines 50 to 53), although I will look into what netgen is doing.

@Tim Edwards point(2), I build two resistors using

res_xhigh_po

in XSCHEM and draw it a layout in MAGIC by using layer xpolyres as shown .The LVS is passed successful here. FYI

This looks like a netgen error; it is doing a series combination of the layout resistors across the pin, which it should not be allowed to do. I will debug it, and hopefully it will get fixed and you won't have to use a modified setup file in the future. (Edited: Incorrect analysis; The problem was much simpler. See comment below.)

@Tim Edwards Thanks for the fast response. I believe Calibre has a rule that specifies whether to do series or parallel reduction first.

LVS REDUCTION PRIORITY {PARALLEL | SERIES}

There may be a mismatch if only one side needs to be reduced. For example, a simple 2 resistor loop with one port can be series reduced to a resistor with both terminals connected to the port or parallel reduced to a resistor with one floating port.

@Mitch Bailey: Netgen still does very complicated reduction of networks, being careful not to reduce either side more than is necessary to match the other side. The part that I fixed happens late in the game, when it has decided that the only way to get a match is to completely collapse the network (or part of it) on one side. Your example is pathological, so I would insist that anything strange like that, if intentional, should just be specified exactly in both the schematic and layout, and then it will match without netgen attempting to do any reduction. The problem above could have also been solved by explicitly drawing the four series resistors in the schematic, but this is a normal case that I think netgen should just be able to handle gracefully.