Art Scott
05/08/2022, 10:22 PMhttps://calligotech.com/products/?tab=activityRaul Murillo achieved significant reductions in the chip area and total logic delay of posit functional units, presented at CoNGA 2022, by exploiting the simplifications that 2's complement format provides (like Yonemoto did, five years ago). Further optimizations are possible, especially if the operations are not required to execute in constant time....'