From John Gustafson -- '...Ananth Kinnal, founder and CEO of CalligoTech in Bangalore, tells me they are making a multicore RISC-V chip in VLSI (not an FPGA) and will have 100 samples by the end of the year. Some of the cores use floats, others use posits, making it quite easy to choose which format you want to experiment with… but the speed should be very comparable to current-generation microprocessors for both formats.

https://calligotech.com/products/?tab=activity

Raul Murillo achieved significant reductions in the chip area and total logic delay of posit functional units, presented at CoNGA 2022, by exploiting the simplifications that 2's complement format provides (like Yonemoto did, five years ago). Further optimizations are possible, especially if the operations are not required to execute in constant time....'