Art Scott
05/02/2022, 9:50 PMArt Scott
05/08/2022, 1:41 PMArt Scott
05/08/2022, 10:22 PMhttps://calligotech.com/products/?tab=activityRaul Murillo achieved significant reductions in the chip area and total logic delay of posit functional units, presented at CoNGA 2022, by exploiting the simplifications that 2's complement format provides (like Yonemoto did, five years ago). Further optimizations are possible, especially if the operations are not required to execute in constant time....'
Art Scott
05/09/2022, 1:13 PMTim Edwards
05/09/2022, 7:07 PMArt Scott
06/09/2022, 2:42 PMArt Scott
06/27/2022, 3:45 PMArt Scott
06/28/2022, 4:20 PMArt Scott
02/19/2023, 2:30 PMTo view this discussion on the web visit https://groups.google.com/d/msgid/unum-computing/7FBE2B07-320B-45B9-AA87-66CF3D62C5E9%40earthlink.net.
Art Scott
02/19/2023, 2:32 PMArt Scott
03/11/2023, 1:55 PMArt Scott
04/01/2023, 1:04 PMArt Scott
05/02/2023, 5:46 PMArt Scott
05/07/2023, 3:11 PMArt Scott
06/27/2023, 3:39 PMArt Scott
08/11/2023, 10:59 AMArt Scott
08/22/2023, 11:02 PMArt Scott
08/26/2023, 1:10 PMArt Scott
09/08/2023, 10:09 AMArt Scott
09/12/2023, 1:54 AMArt Scott
09/28/2023, 10:36 AMWire{6:0v}
is roughly equivalent to wire [6:0]
• Wire{12:1v}
is roughly equivalent to wire [12:1]
• SingleWire is aliased to Wire{0:0v}
, roughly equivalent to wire
On wire arrays
Do the natural thing and use the non-initializing Array{Wire{<descriptor>}}(n)
constructor from Julia. Note that when transpiling to verilog, the wire arrays will be down-shifted by one to make them one-indexed (this feature may change in the future!). Currently, binary muxes are not supported.
Gotchas:
• Assigning to wire array member partials is not allowed:
• my_array = Array{Wire{1:0v},1}(6)
• my_array[1] = Wire(0b11,2) # <== this is OK.
• my_array[2][1:0v] = Wire(0b11,2) # <== don't do this.
•
• Assigning wire array member partials with a function is not allowed:
• my_array[3][1:0v] = some_verilog_module(some_input) # <== don't do this.Angelo Bulfone
10/21/2023, 1:28 AMa xor (0 | -1)
= a * (1 | -1) + (0 | -1)
(where (0 | -1)
and (1 | -1)
denote the format of the sign for the operation), are there any algebraic manipulations that could be done to eliminate them?Angelo Bulfone
10/21/2023, 1:34 AM(exp_x ^ sign_x(0 | -1) + exp_y ^ sign_y(0 | -1) + correction) ^ sign_res(0 | -1)
(from the multiplication logic) to (exp_x * sign_y(1 | -1)) + (exp_y * sign_x(1 | -1)) + (sign_x(0 | 1) * sign_y(1 | -1)) + (sign_y(0 | 1) * sign_x(1 | -1)) + (correction * sign_res(1 | -1)) + sign_res(0 | -1)
, but I'm not sure if it can be simplified back down to something less than the original.Mohammed Fayiz Ferosh
10/23/2023, 2:05 AMAngelo Bulfone
11/06/2023, 12:54 AMs xor a xor b xor c xor s
can reduce to a xor b xor c
.
I don't know how FPGAs work, but they seem to use LUTs more than primitive logic gates, so maybe this doesn't actually help in that context.Angelo Bulfone
11/06/2023, 12:56 AM(a xor s) xor (b xor s) xor (c xor s) xor s = a xor b xor c xor s xor s xor s xor s = a xor b xor c
.Angelo Bulfone
11/06/2023, 2:20 AMAngelo Bulfone
11/06/2023, 2:59 AMArt Scott
11/12/2023, 2:10 PMArt Scott
11/12/2023, 2:26 PM