set the channel description: Topic Open Posit Standard Document (2022) Posithub.org Description Posit Arithmetic Tools and Implementations: Unum & Posit Knowledge Hub Created by Art Scott on April 28, 2022

set the channel topic: Open Posit Standard Document (2022) Posithub.org

set the channel description: Posit Arithmetic Tools and Implementations: Unum & Posit Knowledge Hub Created by Art Scott on April 28, 2022

set the channel description: Posit Arithmetic Tools and Implementations: Unum & Posit Knowledge Hub

set the channel description: Posit Arithmetic Tools and Implementations: Unum & Posit Knowledge Hub https://posithub.org/khub

Better Answers. Fewer bits.

Next Generation Arithmetic Conference on Next Generation Arithmetic (CoNGA) is the leading conference on emerging technologies for computer arithmetic. ‘The impact of the next-generation arithmetic is similar to that of a turn of Moore’s law – doubling computing capability but without having to shrink transistors. Current floating-point numbers (“floats”) were standardised in the 1980s when transistors were millions of times more expensive than they are now; floats make compromises that are overdue for update. The ability to train neural networks with fewer bits (≤16 bits) provides an enormous performance boost for artificial intelligence (AI), presently the most important computing focus and challenge. Novel arithmetic is a game changer for the computing industry. The game in High Performance Computing (HPC) presently is to achieve exascale computing, which most practitioners implicitly assume means a billion double-precision floating-point operations per second while meeting the critical power envelope challenge of staying under 20 MW. The ability of the new generation arithmetic to use fewer bits for the same/higher computation accuracy will facilitate meeting both the performance and power challenges of exascale computing. Unum arithmetic, in particular the newest type of unums (posits), is an example of a disruptive new format. Posits were designed at the request of the RISC-V committee. They have higher accuracy and a larger dynamic range using the same number of bits, or what is perhaps more disruptive, sufficient accuracy using fewer bits, thereby saving storage, bandwidth, energy and power. Posits produce bitwise-identical results across diverse computer systems; current floats cannot even guarantee identical results on successive program runs. To a large extent, posits can serve as drop-in replacements for floats of the same precision; however, the advantages of increasing speed while lowering chip area, power/energy consumption, storage, and bandwidth demands come from using posits to reduce precision requirements without sacrificing accuracy. Changing arithmetic however affects the entire hardware-software stack from chip design to the application. The Conference on Next Generation Arithmetic provides an excellent opportunity for computer arithmetic enthusiasts to gather, interact and exchange ideas on not only what the next generation arithmetic should be, but also the news and updates on the latest developments of breakthroughs with next generation data formats and their corresponding hardware, tools, applications, services, etc..’ Stanford Seminar, Beyond Floating Point: Next Generation Computer Arithmetic https://www.linkedin.com/feed/update/urn:li:activity:6823778113026174976/ “The posit number format is proving ideal for Machine Learning and is now in use by dozens of institutions, both commercial and academic. … it is not beholden to any commercial vendor and utterly non-proprietary…” Type III Unum (Posit & Valid) and Implementations https://en.wikipedia.org/wiki/Unum_(number_format)#Type_III_Unum_(Posit_&_Valid)

set the channel topic: Discussion channel Open Posit Standard Document (2022) Posithub.org

From John Gustafson -- '...Ananth Kinnal, founder and CEO of CalligoTech in Bangalore, tells me they are making a multicore RISC-V chip in VLSI (not an FPGA) and will have 100 samples by the end of the year. Some of the cores use floats, others use posits, making it quite easy to choose which format you want to experiment with… but the speed should be very comparable to current-generation microprocessors for both formats.

https://calligotech.com/products/?tab=activity

Raul Murillo achieved significant reductions in the chip area and total logic delay of posit functional units, presented at CoNGA 2022, by exploiting the simplifications that 2's complement format provides (like Yonemoto did, five years ago). Further optimizations are possible, especially if the operations are not required to execute in constant time....'

https://github.com/arunkmv/perc Posit Enhanced Rocket Chip This is a fork of the Rocket Chip Soc Generator that provides support for posit arithmetic. This has been enabled by utilizing the F and D standard RISC V ISA extensions for floating point arithmetic. The instructions are implemented by the Posit Processing Unit (PPU)/PositFPU which replaces the inhouse IEEE 754 2008 FPU. For more information on posit arithmetic: Posit Hub Unum-computing Google group For more detailed information, please refer to our paper.

@Tim Edwards has left the channel

Weather and climate models are based on 64bit double precision floating-point arithmetic. Recent studies show that floats with only 32bit (single precision) or even less allow for accurate weather forecasts. However, floats might not be the best bit-wise representation of real numbers in the wider field of computational fluid dynamics. Posit numbers are a recently proposed alternative floats and although no standardised posit processor exists yet, we emulate posit arithmetic with a Julia-based emulator on a conventional CPU. A medium complexity atmosphere/ocean circulation model written in Julia is shown to be as accurate with 16bit posits as with 64bit floats. The results are promising for weather and climate models being largely based on 16bit computations with a great potential speed-up on specialised hardware in the future.

The goal of the Universal Numbers Library is to offer applications alternatives to IEEE floating-point that are more efficient and mathematically robust. The motivation to find improvements to IEEE floating-point had been brewing in the HPC community since the late 90's as most algorithms became memory bound and computational scientists were looking for alternatives that provided more granularity in precision and dynamic range. Even though the inefficiency of IEEE floating-point had been measured and agreed upon in the HPC community, it was the commercial demands of Deep Learning that provided the incentive to replace IEEE-754 with alternatives, such as half-floats, and bfloats. These alternatives are tailored to the application and yield speed-ups of two to three orders of magnitude, making rapid innovation in AI possible. The Universal library is a ready-to-use header-only library that provides plug-in replacement for native types, and provides a low-friction environment to start exploring alternatives to IEEE floating-point in your own algorithms. https://github.com/stillwater-sc/universal

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Subject: Re: Need help figuring out a way to convert IEEE 754 representation to Posit To: Unum Computing <unum-computing@googlegroups.com> Note: This is untested and "just a guess". On Saturday, February 18, 2023 at 4:41:05 PM UTC-6 johngustafson wrote: My approach in converting a float to a posit is to first separate the sign from the magnitude (note the sign, then set the bit to zero); then check if the magnitude is zero, in which case return posit zero (all 0 bits). I would separate into S, E, and 1.F (I am a HW guy so this is the way I think) Access a table[E] containing {pE, pEs, pF} pE is the posit regime+exponent, pF is a shift applied to 1.F to put it in the proper position in the posit. pFr = pF > 0 : 1.F >> pF /*you could add rounding on the bits falling off the end here */ : 1.F << -pF; Now:: p = {S<<63 | pE << pEs | pFr}; is the posit when no boundary conditions are encountered. Now we make the table values handle certain special cases:: E = all 1s -> {NaN or Infinity} pF = 63 (thus the shift will eliminate all 1.F bits without making shifters on various architectures cranky) E = all 0s -> denormalized {and I don't remember what posits do with denorms} The table[2048] is easy to construct. Using E directly as an index to the table eliminates having to understand the bias, it is just mapping E to pE<<pEs. If you are going to have to consume (blow) a doubleword for regime+exponent then you can eliminate the shift (saving an instruction (below)). Milan Kloewer's use of posits has in a very restricted range, so his table[E] will hardly damage his cache's data footprint. He may ignore infinities and underflow conditions due to his restricted range. In my ISA, this is 14 instructions (less rounding). Best, John Mitch

https://www.comp.nus.edu.sg/~wongwf/papers/CONGA23-Bedot.pdf Posted in #general

From: 方超 <fantasysee@gmail.com> Date: Sun, May 7, 2023, 2:07 AM Subject: Open-Source Posit Dot-Product Unit (PDPU) for Deep Learning Applications: A Presentation at ISCAS 2023 To: Unum Computing <unum-computing@googlegroups.com> Dear colleagues, We are excited to share with you our latest work on "*PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications*", which will be presented at the 2023 IEEE International Symposium on Circuits and Systems (ISCAS) on Tuesday, May 23rd. Our research team at Nanjing University, consisting of Qiong Li, Chao Fang, and Zhongfeng Wang, will be presenting this exciting project in the Data Path & Arithmetic Circuits & Systems Session. You can find our paper and slides through the provided links. PDPU is a highly efficient hardware module that performs the dot-product operation of two input vectors Va and Vb in low-precision format, accumulating the result and previous output acc to a high-precision value out. This allows for more efficient computation and improved performance for deep learning applications, which often involve a large number of dot-product operations. Our proposed PDPU comes with several features and contributions. Firstly, it implements efficient dot-product operations with fused and mixed-precision properties. This leads to significant reductions in area, latency, and power consumption, up to 43%, 64%, and 70% respectively, compared to discrete architectures. Secondly, it is equipped with a fine-grained 6-stage pipeline that minimizes the critical path and improves computational efficiency. The structure of PDPU is detailed by breaking down the latency and resources of each stage. Lastly, a configurable PDPU generator is developed to enable PDPU to flexibly support various posit data types, dot-product sizes, and alignment widths. We believe that PDPU can make a significant contribution to the field of posit arithmetic units and deep learning. We encourage you to explore the provided links to learn more about our research and to use and contribute to the open-source code. If you have any questions or comments, please feel free to reach out to us. Best regards, Chao Fang