Mitch Bailey02/27/2022, 5:19 PM
and add diodes in the netlist • Correct diode connections in the netlist • Removed some unused resistance from the layout and netlist in the io cells • Fix the DIODE layer in the io cells to only cover the diodes • Make the
netlist match the layout • Change all but 1
in the netlist • Short
in the netlist (need to add SUBCUT somewhere in the layout). • Modify netgen to flatten cells with mismatched terminals instead of adding proxy ports • Black box the
because don’t have all the netlists. • Modify the sram netlist subcircuit names so they don’t clash (i.e.
, etc.) I thinks that’s all. Takes about 5.5 hours to extract and 1.5 hours for compare. I’ll continue to look into the where
are shorting. So the things that may need to be checked on your side are the
mismatches. The only obvious CVC-RV errors were the open logic-analyzer inputs.