@mkk @Tim Edwards @mshalan I finally got caravel to "pass" device level LVS with magic 8.3.270, netgen 1.5.215(base), magic rules sky130A.tech 1.0.264-0-g27ecf1c . Sample data was slot-001 from mpw4. These are the steps I took: • Modify the extraction rules to copyup SUBCUT and DNWELL • Add SUBCUT to io cells • Flatten the io cells when reading the GDS. • Create

sky130_fd_io__gnd2gnd_120x2_lv_isosub

and add diodes in the netlist  • Correct diode connections in the netlist • Removed some unused resistance from the layout and netlist in the io cells • Fix the DIODE layer in the io cells to only cover the diodes • Make the

simple_por

netlist match the layout • Change all but 1

gpio_defaults_block

to

gpio_defaults_block_0403

in the netlist • Short

vssd_core

and

vssd1_core

in the netlist (need to add SUBCUT somewhere in the layout). • Modify netgen to flatten cells with mismatched terminals instead of adding proxy ports • Black box the

user_project_wrapper

because don’t have all the netlists. • Modify the sram netlist subcircuit names so they don’t clash (i.e.

bitcell_array

, etc.)   I thinks that’s all. Takes about 5.5 hours to extract and 1.5 hours for compare.  I’ll continue to look into the where

vssd_core

and

vssd1_core

are shorting. So the things that may need to be checked on your side are the

gpio_default_block

and

simple_por

mismatches. The only obvious CVC-RV errors were the open logic-analyzer inputs.