Looks like the mgmt_core and other caravel logic is mostly on

vssd_core

substrate while the

user_project_wrapper

is on

vssd1_core

(at least for slot-001 of mpw-4). I'm thinking about surrounding the whole

user_project_wrapper

with

SUBCUT

at the caravel level. Since

user_project_wrapper

contains

dnwell

I can't use my modified rules as they are (

SUBCUT

can't operlap

dnwell

). In order to get the gpio cells to extract correctly, I made some pretty scary

SUBCUT

polygons. I think I can change the rules so that

SUBCUT

and

DNWELL

can overlap in the GDS and have the actual connection layers not overlap. May take some more work to make it a valid file for magic editing.