Hello @Mitch Bailey, I am sure this is something silly, but I am struggling to figure out what the LVS issue here is and I was wondering if perhaps you could help? I have a moc design (just an AND gate std cell and a few resistors) that I’ve put in the wrapper. What is crazy to me is that I had this passing a few weeks ago (after your previous help 🙂), but I needed to make a change and somewhere in there I broke something. LVS on the moc-design passes. LVS on the wrapper fails with the AND gate in the moc-design. Running a

diff

between the outputted spice netlists of the moc-design and the wrapper from magic shows no difference in the AND gates. And I verified that the netlists from xschem are both looking at the correct spice subckt definition for the AND gate. It seems like from the netgen output that VPWR is routed incorrectly in magic, but I look at the spice file and I can’t find the mistake. The netgen command I am using shown below with pathing truncated (I’m using a makefile that takes a variable component):

netgen -batch lvs "./xschem/$(component).spice $(component)" "./mag/$(component).spice $(component)" .../netgen/sky130A_setup.tcl ./netgen/$(component)_comp.out

I have attached the wrapper xschem spice, wrapper magic spice, comparison output. Thank you so much! Micah