Hi <@U016HSAA3RQ> For the submitted one, we have n...
# reram
Hi @User For the submitted one, we have no drc with updated precheck on Efabless portal, but it still failed consistent check related to vccd1 (the extracted netlist doesn’t see the vccd1 connects to the caravel but mprj/vccd1). I’m not sure guessing that the reason is because the vias is extracted as a cell then it shows disconnected? @User pls can you suggest how to fix it? I’m also doing place&route the small fabric (2x3 CLB with 1k rram cells). It may need a day to finish then stitch it to the caravel. Is possible to update our design during the weekend? Thanks