I have a question regarding timing constraints on a reset synchronizing chain that will asynchronously assert reset and synchronously deassert. I experienced the following timing failures in the min / hold report

===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: rst (input port clocked by pclk)
Endpoint: _123912_ (removal check against rising-edge clock pclk)
Path Group: **async_default**
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock pclk (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 v input external delay
                  0.02    0.01    4.01 v rst (in)
     1    0.00                           rst (net)
                  0.02    0.00    4.01 v hold537/A (sky130_fd_sc_ls__clkbuf_1)
                  0.05    0.08    4.09 v hold537/X (sky130_fd_sc_ls__clkbuf_1)
     1    0.01                           net4802 (net)
                  0.05    0.00    4.09 v input3/A (sky130_fd_sc_ls__clkbuf_8)
                  0.02    0.12    4.21 v input3/X (sky130_fd_sc_ls__clkbuf_8)
     1    0.00                           net3 (net)
                  0.02    0.00    4.21 v hold536/A (sky130_fd_sc_ls__clkbuf_4)
                  0.03    0.11    4.32 v hold536/X (sky130_fd_sc_ls__clkbuf_4)
     1    0.00                           net4801 (net)
                  0.03    0.00    4.32 v hold6222/A (sky130_fd_sc_ls__clkbuf_4)
                  0.13    0.19    4.50 v hold6222/X (sky130_fd_sc_ls__clkbuf_4)
     3    0.06                           net10487 (net)
                  0.14    0.02    4.52 v _056839_/A (sky130_fd_sc_ls__inv_2)
                  0.04    0.06    4.58 ^ _056839_/Y (sky130_fd_sc_ls__inv_2)
     1    0.00                           _020540_ (net)
                  0.04    0.00    4.58 ^ hold539/A (sky130_fd_sc_ls__clkbuf_1)
                  0.04    0.08    4.66 ^ hold539/X (sky130_fd_sc_ls__clkbuf_1)
     1    0.00                           net4804 (net)
                  0.04    0.00    4.66 ^ _123912_/SET_B (sky130_fd_sc_ls__dfstp_1)
                                  4.66   data arrival time

Now, if this were a typical FF in the design that I wanted to reset, I see this timing error as an issue, but since the FF is in the synchronizer, can the ARst going to these FFs have a TIG constraint applied to them? If so, how would you write a TIG constraint from the input

rst

to the randomly numbered FF's

SET_B

pin? Regardless of the answer to the first, I am generally curious about this second question. Thanks.