Hello everyone, for our chip we use two analog macros and one digital macro. One of the analog macros use 3.3V transistors in the design. We wrapped all the three in Openlane and the flow passed without any DRC violations. But while doing precheck in efabless website, Klayout FEOL check shows 164 DRC violations. All the violations happen in one specific Analog Macro which used HV transistors. I noticed from the .xml file, that three DRC rules called capm.2b, hvntm.1, hvi.2a are getting violated. I have attached a snip shot of xml file, precheck log and analog macro gds. Can someone elaborate on what these rules check and how to overcome this?