@User have you posted schematics of your test setup anywhere? One question I was thinking while looking over the data is how the FPGA interfaces with the RAM during read/write (or vice-versa) as you shmoo the voltage. For example on the Jan 10 plots when the voltage is 1.4V (Maybe VCCD?) what is the voltage on the bank of the FPGA IO block? also 1.4V? The higher level question that I’m alluding to is, are you sure the skew between bits was maintained as voltage was varied? Just floating a theory as to why those fails might be frequency dependent.