@User: I believe that they are related to the change I made because you found that different number of decap cells in the layout vs. schematic were passing through netgen undetected. It appears that the change I made interacts badly with another optimization I made a while ago to treat similarly-connected devices with unconnected pins as parallel devices. I'd have to take a look at it. It's not clear to me why netgen thinks the pins like VBP are unconnected in one of the circuits.