Making some actual progress with

caravel_user_project_analog/xspice

...

example_por_tb.sch

works with variable names. I also got

analog_wrapper_tb.sch

to build a netlist and simulate, but for some reason, the

plot V(io_out[11]) V(io_out[12]) V(io_out[15]) V(io_out[16])
+ V(gpio_analog[3]) V(gpio_analog[7])

statement is so offensive that it prevents the

code_shown.sym

box from getting expanded into the SPICE netlist. Which undocumented implicit assumption that creates an incompatibility between abstraction layers is the problem here? Seems that some parser can't handle "special" characters, probably square brackets.