With schematic level simulation and layout expansion, extraction, and

ext2spice lvs

working for

user_analog_project_wrapper

, I've tried using

netgen

for

lvs user_analog_project_wrapper.spice user_analog_project_wrapper.xschem.spice

. Not unexpectedly the resulting

comp.out

throws lots of errors back at me [link to github, not quote, to reduce clutter in slack at least a little]. To what extent is

user_analog_project_wrapper

from the

caravel_user_project_analog

even supposed to become LvS clean? Do I fail to specify a top level cell to do LvS against in

netgen

?? If

user_analog_project_wrapper

can't be expected to pass LvS, what is the highest level cell in the hierarchy that should pass LvS??? (This is still the unmodified example circuit, to keep configuration problems and my own circuit design problems separate.)