For people that might go to the same path as me: I am trying to put an GPIO cells w/ RING that directly connect to pads: gpio_noesd and io_analog. As my design is all digital and only GPIO cells are analog, I am trying to use OpenLane. Cadense/ Fusion tools handle all of this properly. 1. My main problem was that yosys will connect inouts to TIE-LO cells. According issue is created on openlane repo, and I am working on a fix. Temporary, I am planning to place blockages, and not have inout pins in DEF/Verilog, so it wont try to route them. 2. Using the DEF with v0.23 does not work, as the router crashes with segfault, probably fixed in new openroads 3. Newer OpenLanes dont handle DEFs properly, according issue is created. a. They will copy all the pins, even ones that dont exist on Verilog b. Newer version, dont even create the pins from DEF 4. OpenLane will complain about not being able to route your signals, if signal pins are on layers that do not match the direction they are located on. 5. If LEF has pins with USE set to ANALOG, router errors out. Even if routing of this pin is not required 6. OpenLane cant route analog signals, as expected. Solution I am trying: Make macros with routing, or add blockages on routing, then after final GDS is ready just copy the routing onto it. 7. Caravan's noesd pins are too narrow, IDK if this is going to be an issue when I am driving 50ma thru it. 8. The caravan user project has pins on bottom left, so I cant place my ring and GPIO cells there, as it will interfere with WishBone Pins. No workaround. One more option I am exploring is making a OpenLane macro, with top pins that connect to GPIO. Then manually connecting the pins to my macros.