Hi @User, hope you are doing well. Sorry for my late reply. I have updated the repository of our CAD tool "Fabulous" at https://github.com/FPGA-Research-Manchester/FABulous . Now the tool is ready for both VHDL and Verilog backend. Please don't hesitate to ask if you have any questions or anything you would like to see. Nguyen is currently working on the pdk.