Hi <!channel> We’ve just done our implementation for the first version of FABulous FPGA with sky130 PDK and Cadence Innovus. The fabric consists of 1440 LUT4s (180x CLBs) and 180 LUT5s (45x RegFiles) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version. You can check it out at https://github.com/FPGA-Research-Manchester/eFPGA---RTL-to-GDS-with-SKY130 Please feel free to ask any question/comments.