I've had to fix a couple of bugs in our VHDL -> Verilog conversion process, but I have something that simulates in verilator. I put it up at https://ozlabs.org/~anton/microwatt-20201203.v

module toplevel(ext_clk, ext_rst, uart0_rxd, uart0_txd);

A quick test with yosys suggests its 1.1M gates in CMOS2, but that includes 8kB icache, 8kB dcache, an FPU and 8kB of memory. We can start cutting it down, but where do we want to end up? (I think I heard 900k gates on our call)