Anton Blanchard
01/02/2021, 10:38 PMAnton Blanchard
01/03/2021, 2:06 AMDIODE_INSERTION_STRATEGY=0
worked around it for nowAnton Blanchard
01/07/2021, 9:59 AM----------------------------------------
P-diff distance to N-tap must be < 15.0um (LU.3)
----------------------------------------
5.655 1006.635 5.915 1007.505
6.505 1006.635 6.765 1007.505
7.035 1006.635 7.295 1007.505
Anton Blanchard
01/07/2021, 10:01 AMAnton Blanchard
01/13/2021, 10:57 AMLVS Summary:
Source: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs_parsed.lef.log
net count difference = 0
unmatched nets = 0
Total errors = 1
The only issue I can see is one pin appears twice:
io_oeb[27] |io_oeb[27]
io_oeb[27] |(no matching pin)
...
Cell pin lists for user_project_wrapper and user_project_wrapper altered to match.
The top level cell failed pin matching.
Anton Blanchard
01/14/2021, 8:10 PMsky130_ef_sc_hd__fakediode_2
. For now I'm just converting them to a sky130_fd_sc_hd__diode_2
.Anton Blanchard
01/19/2021, 8:31 AMmshalan
01/20/2021, 10:15 PMAnton Blanchard
01/20/2021, 10:17 PMmshalan
01/21/2021, 8:21 AMAnton Blanchard
01/21/2021, 10:28 AMAnton Blanchard
01/29/2021, 10:41 AMAnton Blanchard
02/03/2021, 7:36 AMmshalan
03/03/2021, 8:57 PMAnton Blanchard
03/04/2021, 6:11 AMAnton Blanchard
03/04/2021, 6:12 AMAnton Blanchard
03/05/2021, 11:23 AMmax_capacitance/capacitance
for the Z pin is 33-39 depending on the gate size (wire capacitance would bring that down I presume).
I'm not sure how much of an issue this is in practice. Would it just affect frequency, or are there other potential issues?mshalan
03/05/2021, 11:25 AMAnton Blanchard
03/05/2021, 11:33 AMAnton Blanchard
03/05/2021, 7:25 PMAnton Blanchard
03/05/2021, 7:25 PMmshalan
03/05/2021, 7:28 PMAnton Blanchard
03/05/2021, 7:33 PMmshalan
03/09/2021, 1:44 PMmshalan
03/09/2021, 1:45 PMAnton Blanchard
03/09/2021, 8:11 PMAnton Blanchard
03/09/2021, 8:11 PMEdevaldo
04/14/2021, 12:02 AMstefanoaz
06/13/2021, 12:34 AMSiddharth Joshi
10/24/2021, 1:06 AM