My conversion is simple: I have several small blocks that I convert to a generic verilog netlist (with yosys) and write it. Then I use the normal OpenLANE flow. The best advice I can give is to use small blocks and harden them as macros. This makes the process rather quick (a couple of minutes) and allow you to iterate quickly. If you have big blocks, it might take hours which could be wasted in case of failure or errors. ghdl keeps the hierarchy of your modules. So you can split your design and optimize locally.