@User: Yes, although I need to make sure I'm watching the process of the board development carefully to make sure that happens the way I intended. I did not specify GPIOs for the IO2 and IO3 connections because they are not relevant to the verilog RTL, but they should be connected to the two GPIOs above the ones used for IO0 and IO1 (which would then map mprj_io[12] = IO2 and mprj_io[13] = IO3). I should note that on the documentation even if it is not in the verilog.