For hardening the design, I just copied user_proj_example.v and replaced the contents with my own project and tweaked the config.tcl (WIP, does not pass DRC and probably has other problems). That included the power connections which, like the example, aren't actually wired to anything in the verilog. Would also like to confirm if we do or don't have to do anything special with them: https://github.com/dan-rodrigues/caravel/blob/vdp-lite/verilog/rtl/vdp_lite_user_proj.v#L8 Precheck README states Caravel is meant to be the benchmark presumably with the included user project so I'm following the model it provides unless I'm told otherwise.