In synthesis of my user_project_wrapper, I get the following warning

Warning: Module $paramod$86ee6077fd23a04b01bd50a3e77717e9daf7577f\sha3_256_miner_regs contains unmapped R

TLIL processes. RTLIL processes can't always be mapped directly to Verilog always blocks. Unintended

Am I using unsupported verilog syntax?