Tim Edwards

11/30/2020, 10:11 PM
The documentation (datasheet) shows a region belonging to vdda1/vssa1,vccd1/vssd1 and vdda2/vssa2,vccd2/vssd1. This region indicates the extent to which those signals extend around the padframe on the padframe buses. But the pads themselves are driven by vddio/vssio and the 1.8V logic in the pads is driven by vcchib/vssd. I considered whether I should have the user-facing circuit on the GPIO control block be on vccd2/vssd2 in that region, but eventually I decided that it was better to just keep all the GPIO control circuits in one user domain.