Inability to use the management SoC to drive the pads while the user project simultaneously reads the pad values. This "feature" was sort of implied by some simplified diagrams I made but didn't actually exist; the GPIOs were set up to be used by the management SoC or the user project but not both at the same time. Since it is a useful feature to have, though, I worked it in. The first attempt failed because the synthesis tool decided to put two tristate buffers in series, and we didn't detect that until running gate-level simulation, late in the game. But we are now revisiting some of the layout after doing a design review yesterday (mostly bulking up the power supply lines), and we will pull in the fix for this after all.