Hopefully this is a non-issue. The storage module contains 2 instances of

sram_1rw1r_32_256_8_sky130

, SRAM_0 and SRAM_1. SRAM_1 has unconnected inputs that may be Hi-Z input to logic (particularly

clk1

looks like it's input to an inverter). Here is the verilog from

verilog/rtl/storage.v

sram_1rw1r_32_256_8_sky130 SRAM_0 (
  .addr0(mgmt_addr),
  .addr1(mgmt_addr_ro),
  .clk0(mgmt_clk),
  .clk1(mgmt_clk),
  .csb0(mgmt_ena[0]),
  .csb1(mgmt_ena_ro),
  .din0(mgmt_wdata),
  .dout0(mgmt_rdata[31:0]),
  .dout1(mgmt_rdata_ro),
  .gnd(VGND),
  .vdd(VPWR),
  .web0(mgmt_wen[0]),
  .wmask0(mgmt_wen_mask[3:0])
 );
 sram_1rw1r_32_256_8_sky130 SRAM_1 (
  .addr0(mgmt_addr),
  .addr1({ _NC1, _NC2, _NC3, _NC4, _NC5, _NC6, _NC7, _NC8 }),
  .clk0(mgmt_clk),
  .csb0(mgmt_ena[1]),
  .din0(mgmt_wdata),
  .dout0(mgmt_rdata[63:32]),
  .dout1({ _NC9, _NC10, _NC11, _NC12, _NC13, _NC14, _NC15, _NC16, _NC17, _NC18, _NC19, _NC20, _NC21, _NC22, _NC23, _NC24, _NC25, _NC26, _NC27, _NC28, _NC29, _NC30, _NC31, _NC32, _NC33, _NC34, _NC35, _NC36, _NC37, _NC38, _NC39, _NC40 }),
  .gnd(VGND),
  .vdd(VPWR),
  .web0(mgmt_wen[1]),
  .wmask0(mgmt_wen_mask[7:4])
 );

You can notice that SRAM_1 is missing the following inputs

clk1
csb1

Also

addr[0:7]

are inputs defined as not connected.