Thanks! yes I'm trying to add some memory to my design using the same as in the

mgmt_soc

https://github.com/efabless/caravel/blob/master/verilog/rtl/mem_wb.v, I would like also to read and write memory via wb from firmware, so I assume this would work using almost the same as in

mgmt_soc

. So the most simple way I could get around so far is only with

reg [31:0] RAM[(64*COLS)-1 : 0];

based on DFFRAM repo and some ideas-modifications from microwatt caravel repo, here is my version of it https://github.com/tucanae47/mem_test_caravel/blob/main/src/DFFRAM.v I have trouble understanding that code Matt just pointed out and also there are a few things I'm not sure how to fix, for example, according to the smallest size example I found in DFFRAM repo I need to use

set ::env(DIE_AREA) "0 0 1000 800"

. Here is my current config version https://github.com/tucanae47/mem_test_caravel/blob/main/config.tcl#L13, and the best results after processing-hardening are in the picture but would like to get it smaller, I'm part of the course with Matt and there we only have "300 300" . Also, I'm missing to test exploration tool with area size. (which will be the next step), but if any suggestions or hints please do 🙂