I have some queries. In the Caravel Harness Documentation, it is a bit unclear about the size of the SRAM available. As far as I had seen, the Features list shows that the SoC has 8K word SRAM. And in the SRAM subsection, it is mentioned that the management area SRAM has 256 words (with width 32 bits) and Storage Area SRAM size can be configured. If that's the case, what is the maximum size and number of the Storage Area SRAMs that can be used? And also, please confirm whether the size of management area SRAM is 256 words only or 1K words?