@User: No. The reason for the

_XXXX

variants is that the RTL for those blocks has a parameter defining what default values are being output by the block. If you synthesize

gpio_defaults_block

by itself, then it can only be synthesized with the parameter set to some constant value. Instead of unparameterizing it and having lots of redundant verilog modules for (potentially 2^13 different versions!), I left the parameterized module as-is, synthesized an initial layout, and hand-modified the layout to allow each output bit to be selected 1 or 0 by the placement of a single via. Then I wrote a script that moves vias around to create whatever versions are needed for the chip, and generates a separate layout for each. For that script, the DEF file is not used for anything; it is entirely done with the gate-level verilog and the layout (in magic).