#1067 LVS Mismatch Error New issue created by vijayank88 Description Using OpenLane tag 2022.04.17_01.59.58 fails with LVS. Its MPW5 precheck passed designs. But its failing with LVS stage with above OpenLane tag. Environment

Kernel: Linux v3.10.0-1160.49.1.el7.x86_64
Distribution: centos 7
Python: v3.6.8 (OK)
Container Engine: docker v20.10.13 (OK)
OpenLane Git Version: c29cdb4379acb11b67506b8e43f4d85249297498
pip: INSTALLED
pip:venv: INSTALLED
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PDK Version Verification Status: OK
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Git Log (Last 3 Commits)

c29cdb4 2022-04-18T17:20:57+02:00 Don't call read_verilog if we are reading a DEF (#1051) - Anton Blanchard -  (HEAD -> master, tag: 2022.04.19_01.43.34, origin/master, origin/HEAD)
754b537 2022-04-18T16:46:39+02:00 Fix `get_tag.py` (#1062) - Mohamed Gaber -  ()
85b6cec 2022-04-16T18:04:28+02:00 Fix Jenkins to work with Volare (#1058) - Vitor Bandeira -  (tag: 2022.04.17_01.59.58)

Reproduction Material -Unzip the file FMAC_wrapper.zip -Copy directory

FMAC_wrapper

to OpenLane/designs/ -cd OpenLane -make mount -cd designs/FMAC_wrapper -source run.tcl Expected behavior LVS clean pass Logs

vccd2                                      |vccd2                                      
vdda1                                      |vdda1                                      
vdda2                                      |vdda2                                      
vssa1                                      |vssa1                                      
vssa2                                      |vssa2                                      
vssd2                                      |vssd2                                      
(no matching pin)                          |vccd1                                      
(no matching pin)                          |vssd1                                      
vccd1                                      |(no matching pin)                          
vssd1                                      |(no matching pin)                          
---------------------------------------------------------------------------------------
Cell pin lists for user_project_wrapper and user_project_wrapper altered to match.
Cells failed matching, or top level cell failed pin matching.

[ERROR]: There are LVS errors in the design..
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'runs/RUN_2022.04.22_09.22.08/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'runs/RUN_2022.04.22_09.22.08/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

The-OpenROAD-Project/OpenLane