A Hardware Generator for SORN Arithmetic https://ieeexplore.ieee.org/abstract/document/9049141 This work provides an efficient hardware generator for high-performance Sets-of-Real-Numbers (SORN) arithmetic. Complex datapaths are automatically built in VHDL, comprising the generation of arithmetic operations and functions as well as all necessary interconnects. Various SORN datatypes can be easily set up enabling high adaptivity to different applications. For further performance improvements additional optimization and implementation techniques are considered as well. For evaluation, a SORN-based symbol detector for a multi-antenna wireless communication scenario is generated that solves a system of linear equations. As SORN-based signal processing allows a quick but rough calculation of the system equations outcome, it can be exploited to reject possible input vectors that do not satisfy the general constraints of the signal detection task. Hence, this generally leads to a heavily reduced set of remaining solutions. Multiple hardware architectures with different SORN datatypes are generated and compared. Further, an analysis is performed considering the signal-to-noise (SNR) ratio. Finally, logic synthesis is applied to selected designs and compared to references from the literature highlighting our work to be highly hardware-efficient and suitable for application-specific signal processing.