#246 Add gate level simulation verilog to PDK. New issue created by donnie-j I needed to simulate the gate level netlist for DFFRAM, but I found that no combination of defines results in functional results with icarus verilog and sky130_fd_sc_hd.v as installed by Open_PDK. Defining FUNCTIONAL gets close, but it seems to pull in some behavioural models, which are broken for simulation. Also, the lpflow and spare cell macros cause problems, so they need to be excluded (or fixed). I went back to the SkyWater sources to find the correct models to include, and this is the 'recipe' to create a pure simulation verilog library:

$ (for i in `ls | grep -v lpflow | grep -v macro ` ; do find $i -name \*functional\*v | grep -v \.pp\. ; find $i -name \*_[0-9]*.v  ; done) > lst
$ echo \`define UNIT_DELAY \#1 > sky130_fd_sc_hd_sim.v
$ cat $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v >> sky130_fd_sc_hd_sim.v
$ for i in `cat lst` ; do grep -v ^\`include $i >> sky130_fd_sc_hd_sim.v; echo >> sky130_fd_sc_hd_sim.v; done

This file can then be used very simply to run post synthesis simulations, e.g.:

$ iverilog -o ram_tb sky130_fd_sc_hd_sim.v RAM8.nl.v ram_tb.v ; vvp ram_tb
VCD info: dumpfile ram_tb.vcd opened for output.

RTimothyEdwards/open_pdks