Running openlane on my home mac. Looking at the LVS results for the sample spm design, I noticed that no devices were extracted from the layout. Everything is black boxes. Is this intentional? Is there a way to link the verilog source to lower level CDL and do LVS at the device level? Does the extraction rule file need to be changed to extract devices? Unfortunately, currently the cells extracted with magic and and base CDL cells have different number of pins in different order. magic: output before power, no bulk terminals cdl: output after power, bulk terminals For example: designs/spm/runs/*/results/magic/spm.spice * Black-box entry for subcircuit sky130_fd_sc_hd__and2_4 abstract view .subckt sky130_fd_sc_hd__and2_4 A B X VGND VPWR .ends open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl .SUBCKT sky130_fd_sc_hd__and2_8 A B VGND VNB VPB VPWR X MMP0 Y A VPB phighvt ... MMP1 Y B VPB phighvt ... MMIP0 X y VPB phighvt ... MMN0 y A VNB nshort ... MMN1 sndA B VNB nshort ... MMIN0 X y VNB nshort ... .ENDS sky130_fd_sc_hd__and2_4 ALSO: Please note that the CDL is incorrect! The mosfets have only 3 connections. It looks like the source connections are missing. The source of MMN0 should be sndA and the drain y.