Using rc4 and the following commits, these are the steps I'm taking to get device level LVS to (almost) pass. 1. extract with

mag

views instead of

maglef

views. (Change to

run_magic_spice_export

in

scripts/tcl_commands/magic.tcl

) 2. instead of

netgen -batch lvs

, I execute the following script to add the cdl subcircuit definitions to the verilog netlist.

model blackbox on
readnet spice /openLANE_flow/sky130_fd_sc_hd.v.cdl 1
lvs {$layout $module_name} {$schematic $module_name} $setup_file $output -json

3. The

sky130_fd_sc_hd.v.cdl

is created by copying

sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl

and changing M-devices to X-devices and adding device libraries to model names

sed -e 's/^M/XM/' -e 's/ [np]fet/ sky130_fd_pr__&/' <input> > <output>

Since extraction gives X-devices, the cdl must be modified to match (otherwise the pin names don't match). Currently, the netgen setup file only permutes devices prefixed with library names, so even though netgen compares <model> to <library>__<model>, permuted pins won't match. 4. I've also modified

sky130A/libs.tech/netgen/setup.tcl

to ignore

tapvpwrvgnd

cells. The connectivity has already been extracted and the subcircuits in the netlists are empty. (extracted netlist has no definition, so netgen adds placeholders with default pins. It appears that these don't match the pin names defined in the cdl) 5. The version of magic in the rc4 docker does not extract mosfet with source and drain connected to the same net. decap cells are currently ignored in the netgen setup, so shouldn't break the current LVS. Personal opinion is to keep decap cells in low level LVS (check the number), but that requires a change to

sky130A/libs.tech/netgen/setup.tcl

There may still be some problems with the port numbers in the mag files, but should be fixed soon. I made some other changes to extract mos capacitors and those currently cause property errors, but these should go away with the latest version of magic.