The `zipdiv` design does not pass LVS (abstract or...
# verification-be
m
The
zipdiv
design does not pass LVS (abstract or device level). The circuits are the same, but the ports
o_quotient[2:0]
don't match. Digging through the netlists, it appears that the cause is a buffer placement. I've removed the power connections for sake of brevity.
Copy code
sky130_fd_sc_hd__dfxtp_4 _2916_ (
  .CLK(clknet_4_11_0_i_clk),
  .D(_0002_),
  .Q(o_quotient[0]),
 );
 sky130_fd_sc_hd__inv_8 _2638_ (
  .A(o_quotient[0]),
  .Y(_0596_)
 );
 sky130_fd_sc_hd__buf_2 psn_inst_psn_buff_37 (
  .A(o_quotient[0]),
  .X(psn_net_37)
 );
 sky130_fd_sc_hd__buf_2 psn_inst_psn_buff_38 (
  .A(psn_net_37),
  .X(psn_net_38)
 );
 sky130_fd_sc_hd__nor2_2 _2880_ (
  .A(psn_net_49),
  .B(psn_net_38),
  .Y(_0809_)
 );
In the
zipdiv.lvs.powered.v
file, the latch output
o_quotient[0]
is input to an inverter and a buffer-buffer-nor2 gate.
Copy code
X_2916_ _2927_/CLK _2916_/D _2916_/Q sky130_fd_sc_hd__dfxtp_4
X_2638_ _2916_/Q _2640_/B sky130_fd_sc_hd__inv_8
Xpsn_inst_psn_buff_37 _2916_/Q o_quotient[0] sky130_fd_sc_hd__buf_2
Xpsn_inst_psn_buff_38 o_quotient[0] _2880_/B sky130_fd_sc_hd__buf_2
X_2880_ _2880_/A _2880_/B _2881_/B sky130_fd_sc_hd__nor2_2
In the extracted spice file, the latch output is an internal signal
_2916_/Q
which is buffered to become
o_quotient[0]
.