It looks like `netgen` doesn t

Question

< U016EM8L91B> < U016HSALFAN> It looks like `netgen` doesn t flag any errors if one of the cells has no devices and the other has no devices or nets This is from the caravel `user project wrapper` design There is no definition for the verilog `user proj example` in `user project wrapper synthesis v` so it looks like `netgen` creates one ```Reading netlist file project openlane user project wrapper runs user project wrapper results magic user project wrapper spice Reading netlist file project openlane user project wrapper runs user project wrapper results synthesis user project wrapper synthesis v Contents of circuit 1 Circuit user proj example Circuit user proj example contains 0 device instances Circuit contains 0 nets and 614 disconnected pins Contents of circuit 2 Circuit user proj example Circuit user proj example contains 0 device instances Circuit contains 0 nets Circuit user proj example contains no devices Contents of circuit 1 Circuit user project wrapper Circuit user project wrapper contains 1 device instances Class user proj example instances 1 Circuit contains 614 nets and 32 disconnected pins Contents of circuit 2 Circuit user project wrapper Circuit user project wrapper contains 1 device instances Class user proj example instances 1 Circuit contains 612 nets and 32 disconnected pins Circuit 1 contains 1 devices Circuit 2 contains 1 devices Circuit 1 contains 612 nets Circuit 2 contains 612 nets Netlists match uniquely Result Circuits match uniquely Logging to file project openlane user project wrapper runs user project wrapper results lvs user project wrapper lvs log disabled LVS Done LVS reports no net device pin or property mismatches ``` It looks like LVS passes but if you look at the pin counts for `user proj example` there s a difference of 2 612 vs 614 The verilog does not contain `VPWR` and `VGND`