Mitch Bailey
11/27/2020, 6:44 PMnetgen
doesn't flag any errors if one of the cells has no devices and the other has no devices or nets. This is from the caravel user_project_wrapper
design. There is no definition for the verilog user_proj_example
in user_project_wrapper.synthesis.v
so it looks like netgen
creates one.
Reading netlist file /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/magic/user_project_wrapper.spice
Reading netlist file /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v
Contents of circuit 1: Circuit: 'user_proj_example'
Circuit user_proj_example contains 0 device instances.
Circuit contains 0 nets, and 614 disconnected pins.
Contents of circuit 2: Circuit: 'user_proj_example'
Circuit user_proj_example contains 0 device instances.
Circuit contains 0 nets.
Circuit user_proj_example contains no devices.
Contents of circuit 1: Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 1 device instances.
Class: user_proj_example instances: 1
Circuit contains 614 nets, and 32 disconnected pins.
Contents of circuit 2: Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 1 device instances.
Class: user_proj_example instances: 1
Circuit contains 612 nets, and 32 disconnected pins.
Circuit 1 contains 1 devices, Circuit 2 contains 1 devices.
Circuit 1 contains 612 nets, Circuit 2 contains 612 nets.
Netlists match uniquely.
Result: Circuits match uniquely.
Logging to file "/project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.log" disabled
LVS Done.
LVS reports no net, device, pin, or property mismatches.
It looks like LVS passes, but if you look at the pin counts for user_proj_example
, there's a difference of 2 (612 vs 614). The verilog does not contain VPWR
and VGND
.