<@U016EM8L91B> I have a question about how far net...
# verification-be
m
@User I have a question about how far netgen flattens unmatched cells in the hierarchy. As you know, the gds for the caravel sram module contains cells prefixed with 'pk_'. When I equate these to the corresponding spice cells without the 'pk_' prefix, I expect to get a hierarchical LVS output. Due to well taps, etc. some hierarchies are flattened and match at at higher level. I get the following results for
control_logic_r
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Contents of circuit 1: Circuit: 'pk_control_logic_r'
Circuit pk_control_logic_r contains 174 device instances.
 Class: sky130_fd_pr__nfet_01v8 instances: 87
 Class: sky130_fd_pr__pfet_01v8 instances: 87
Circuit contains 102 nets.
Contents of circuit 2: Circuit: 'control_logic_r'
Circuit control_logic_r contains 114 device instances.
 Class: sky130_fd_pr__nfet_01v8 instances: 54
 Class: pand2_0        instances:  2
 Class: pdriver_2       instances:  1
 Class: pdriver_5       instances:  1
 Class: dff_buf_0       instances:  1
 Class: sky130_fd_pr__pfet_01v8 instances: 54
 Class: pand3_0        instances:  1
Circuit contains 78 nets, and 11 disconnected pins.

Circuit 1 contains 174 devices, Circuit 2 contains 114 devices. *** MISMATCH ***
Circuit 1 contains 102 nets,  Circuit 2 contains 66 nets. *** MISMATCH ***

 Flattening non-matched subcircuits pk_control_logic_r control_logic_r
Flattening instances of pk_control_logic_r in file /openlane/caravel/openlane/storage/runs/lvs/results/magic/storage.gds.spice
Flattening instances of control_logic_r in file /openlane/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
The layout consists of primitives only. The netlist consists of some cells that have been flattened (not shown: delay_chain, pdriver_6, pinv_0, pnand2_1) and cells that have been matched (dff_buf_array_0, pand2_0, pand3_0, pdriver_2, pdriver_5). It appears what netgen attempts to do is to flatten both pk_control_logic_r and control_logic_r into the parent cells. However, I think what needs to be done is to flatten the matched cells in the control_logic_r circuit. Will either of the following netgen commands do this?
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flatten control_logic_r
or
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flatten class control_logic_r dff_buf_array_0
flatten class control_logic_r pand2_0
flatten class control_logic_r pand3_0
flatten class control_logic_r pdriver_2
flatten class control_logic_r pdriver_5
or maybe
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flatten class control_logic_r *