@User I'm looking at the netgen code, trying to figure out how unmatched pins are handled. What happens when the layout has a port that is missing in the source netlist? For example, take a buffer with an

in

,

out

, and

outb

ports in the layout, but only

in

and

out

ports in the source (

outb

is an internal node in the source).

outb

in the layout is not disconnected, but rather unused. It looks like netgen will show

no matching pin

in the LVS report and say

pin lists altered to match

, but it looks like it's creating a proxypin to a new node.