Channels
events
silicon-validation
maker-projects
fossee-iitb-google-sky130
zettascale
sdram
genius-vlsi
pd-openlane-and-sky130
chipignite2206q_stanford_bringup
sky130
vhdl
courses
magic
activity
xschem
generative-ai-silicon-challenge
popy_neel
openroad
openlane
cadence-virtuoso
openlane-development
announcements
ieee-sscs-dc-22
maker-zone
pa-test-chip
fossee-iitb-esim
dynamic-power-estimation
rios
ieee-sscs-dc-23
latam_vlsi
tapeout-job
hardware-beginners
mpw-one-silicon
aa
design-services
private-shuttle
ieee-sscs-cac-23
stdcelllib
b2aws
beagleboard
tapeout-pakistan
rad-lab-silicon
timing-closure
mpw-2-silicon
announce
skywater
fasoc
bag
team-awesome
paracells
cadence-spectre
japan-region
serdes
travis-ci
opentitan
cadence-innovus
strive
infiniband
verification-fe
openocd
riscv
containers
sky65
openfpga
chisel
osu
radio
neuro-mem
help-
electric
dffram
images
microwatt
sky90
sky130-ci
swerv
fault
fpga
mpw-one-clean-short
picosoc
layouteditor
digital-design
junk
researchers
coalition-for-digital-environmental-sustainability
vlsi101
magical
vlsi_verilog_using_opensource_eda
basebands
vlsi_verilog_using_opensoure_eda
toysram
cadence-genus
abcc
fuserisc
vliw
openlane_cloudrunner
bluetooth
design-review
vhdl-learners
digital-electronics-learners
verilog-learners
uvm-learners
ihp-sg13g2
rdircd
discord-mods
gf180
b2aws-tutorial
gf180mcu
system-verilog-learners
vlsi-learners-group
chilechipmakers
foss-asic-tools
silicon-validation-private
chipignite
vh2v
sram
shuttle-status
board-respin
openpositarithmetic
openadiabaticlogic
openhighqualityresonators
venn
xls
rf-mmw-design
nydesign
open-pdk
j-core
power
waveform-viewers
pll
vendor-synopsys
openpower
silicon-photonics
lvs
chip-yard
shuttle
adiabatonauts
openram
funding
community_denmark_dtu
open_pdks
lvs-analysis
xyce
efabless
general
analog-design
klayout
caravel-board
reram
ieee-sscs-dc-21q3
sky130-pv-workshop
shuttle-precheck
caravan
verification-be
caravel
Title
s
Stefan Schippers
12/08/2020, 6:05 PMBasically for every single mos transistor in the design 198 models are saved together with the transistor, and this is repeated for every transistor, while an efficient storage for this circuit requires 1 model per transistor, after expansion.
15890 : m.x5.x1.msky130_fd_pr__pfet_01v8_hvt vcc clk_g x5.a_59_75# vcc ...
15891 : .model x5.x1:sky130_fd_pr__pfet_01v8_hvt__model.0 pmos lmin=2.0e-05...
15893 : .model x5.x1:sky130_fd_pr__pfet_01v8_hvt__model.1 pmos lmin=8.0e-06...
...
...
16285 : .model x5.x1:sky130_fd_pr__pfet_01v8_hvt__model.197 pmos lmin=1.5e-07...